Ing. Jan Bělohoubek, Ph.D.

Publikace

On the Influence of the Laser Illumination on the Logic Cells Current Consumption

Autoři
Petryk, D.; Dyka, Z.; Krstic, M.; Bělohoubek, J.; Fišer, P.; Steiner, F.; Blecha, T.; Langendörfer, P.; Kabin, I.
Rok
2023
Publikováno
Proc. of 30th IEEE International Conference on Electronics, Circuits and Systems. New Jersey: IEEE, 2023. ISBN 979-8-3503-2649-9.
Typ
Stať ve sborníku
Anotace
Physical side-channel attacks represent a great challenge for today’s chip design. Although attacks on CMOS dynamic power represent a class of state-of-the-art attacks, many other effects potentially affect the security of CMOS chips analogously by affecting mostly static behaviour of the chip, including aging, ionizing radiation, or non-ionizing illumination of the CMOS. Vulnerabilities exploiting data dependency in CMOS static power were already demonstrated in practice and the analogous vulnerability exploiting light-modulated static power was demonstrated by simulation. This work confirms the CMOS vulnerability related to the light-modulated data-dependent static power experimentally and discusses future work.

Optically induced static power in combinational logic: Vulnerabilities and countermeasures

Rok
2021
Publikováno
Microelectronics Reliability. 2021, 124 ISSN 0026-2714.
Typ
Článek
Anotace
Physical attacks, namely invasive, observation, and combined, represent a great challenge for today's digital design. Successful class of strategies adopted by industry, allowing hiding data dependency of the side channel emissions in CMOS is based on balancing. Although attacks on CMOS dynamic power represent a class of state-of-the-art attacks, vulnerabilities exploiting data dependency in CMOS static power and light-modulated static power were recently presented. In this paper, we describe structures and techniques developed to enhance and balance the power imprint of the traditional static CMOS bulk structures under invasive light attack. The novel standard cells designed according to the presented techniques in the TSMC180nm technology node were used to synthesize the dual-rail AES SBOX block. The behavior of the AES SBOX block composed of the novel cells is compared to classical approaches. Usage of novel cells enhances circuit security under invasive light attack while preserving comparable circuit resistance against state-of-the-art power attacks.

Standard Cell Tuning Enables Data-Independent Static Power Consumption

Rok
2020
Publikováno
Proceedings of the 23rd International Symposium on Design and Diagnostics of Electronic Circuits and Systems. Piscataway, NJ: IEEE, 2020. ISSN 2334-3133. ISBN 978-1-7281-9938-2.
Typ
Stať ve sborníku
Anotace
Physical attacks, namely invasive, observation and combined, represent a great challenge for today’s digital design. Successful class of strategies adopted by industry, allowing hiding data dependency of the side channel emissions in CMOS is based on balancing. Although attacks on CMOS dynamic power represent a class of state-of-the-art attacks, vulnerabilities exploiting data dependency in CMOS static power and light- modulated static power were recently presented. In this paper, we describe structures and techniques developed to enhance and balance traditional static CMOS bulk structures. To enable data dependency hiding, we propose low-level techniques based on complementary-value induced balancing currents, constant current source behavioral approximation, and light-sensing capability of traditional CMOS structures. The proposed techniques may be used to build a dual-rail circuit balanced from both perspectives: static and dynamic power. The publicly available TSMC180nm node standard cell simulation is used for evaluation.

CMOS Illumination Discloses Processed Data

Rok
2019
Publikováno
Proceedings of the 22nd Euromicro Conference on Digital Systems Design. Los Alamitos, CA: IEEE Computer Soc., 2019. p. 381-388. ISBN 978-1-7281-2861-0.
Typ
Stať ve sborníku
Anotace
As digital devices penetrate to many areas important for the present society, it is important to analyze even potential threats to mitigate vulnerabilities during their lifetime. In this paper, we analyze the data dependency of the photocurrent induced by a laser beam in the illuminated CMOS circuit. The data dependency may introduce potential threat(s) originating in the nature of the CMOS technology. The data dependency can be potentially misused to compromise the data processed by an embedded device. We show that also the devices employing dual-rail encoding to hide data-dependency are not safe.

Using Voters May Lead to Secret Leakage

Rok
2019
Publikováno
Proceedings of the 22nd International Symposium on Design and Diagnostics of Electronic Circuits and Systems. Piscataway, NJ: IEEE, 2019. p. 1-4. ISBN 978-1-7281-0073-9.
Typ
Stať ve sborníku
Anotace
The security of many digital devices strongly depends on a secret value stored in them. To mitigate security threats, high protection of such a value must be provided. Many attacks against (cryptographic) hardware as well as attack countermeasures were presented recently. As new attacks are invented continuously, it is important to analyze even potential threats to mitigate device vulnerability during its lifetime. In this paper, we report a novel voter-related vulnerability, which can be potentially misused to compromise the secret value stored in an embedded device.

Zvyšování spolehlivosti a bezpečnosti číslicových obvodů na úrovni mikroarchitektury

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Rok
2018
Publikováno
Počítačové architektury a diagnostika 2018. Plzeň: Západočeská univerzita v Plzni, 2018. p. 41-44. ISBN 978-80-261-0814-6.
Typ
Stať ve sborníku
Anotace
Spolehlivost a bezpečnost jsou důležité vlastnosti vyžadované od mnoha zařízení. Zvýšení spolehlivosti a bezpečnosti systému lze dosáhnout mimo jiné vhodnou mikroarchitekturou. Dokončený výzkum se věnoval právě zvyšování spolehlivosti číslicových systémů na úrovni mikroarchitektury. Výzkum na něj bezprostředně navazující cílí na řešení spojující přístupy zajišťující zároveň bezpečnost i spolehlivost dílčích částí číslicových systémů. Velká část příspěvku je věnována rešerši, jež se váže k navrhovanému konceptu uTMR.

Error Masking Method Based On The Short-Duration Offline Test

Rok
2017
Publikováno
Microprocessors and Microsystems. 2017, 52 236-250. ISSN 0141-9331.
Typ
Článek
Anotace
The method proposed in this article allows to construct error-masking fail-operational systems by com- bining time and area redundancy. In such a system, error detection is performed online, while error masking is achieved by a short-duration offline test. The time penalty caused by the offline test applies only when an error is detected. The error-masking ability in such a system is very close to TMR, the area overhead is smaller for a well defined class of circuits, and the delay penalty caused by the offline test remains reasonably small. The short-duration offline test is possible only when extensive design-for-test practices are used. Therefore, a novel gate structure is presented, which allows to construct combina- tional circuits testable by a short-duration offline test. The proposed test offers com plete fault coverage with respect to the stuck-on and stuck-open fault model. The proposed solutions are combined and a comprehensive description of the overall error-masking architecture is provided.

Error Correction Method Based on the Short-Duration Offline Test

Rok
2016
Publikováno
Proceedings of 19th Euromicro Conference on Digital System Design DSD 2016. Los Alamitos, CA: IEEE Computer Soc., 2016. p. 495-502. ISBN 978-1-5090-2816-0.
Typ
Stať ve sborníku
Anotace
The method proposed in this paper allows to construct error-correcting systems by combining time and area redundancy. In such a system, error detection is performed online, while error correction uses a short-duration offline test. The time penalty caused by the offline test applies only when an error is detected. The error-correcting ability in such a system is comparable with TMR, the area overhead is smaller for a class of circuits, and the delay penalty caused by the offline test remains reasonably small. The short-duration offline test is possible only when extensive design-for-test practices are used. Therefore, a novel gate structure is presented, which allows to construct combinational circuits testable by a short-duration offline test. The proposed test offers complete fault coverage with respect to the stuck-on and stuck-open fault model.

Využití rychlého offline testu v systému se schopností maskování jedné chyby

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Rok
2016
Publikováno
Počítačové Architektury & Diagnostika PAD 2016 - Sborník příspěvků. Brno: Vysoké učení technické v Brně, 2016. p. 85-88. ISBN 978-80-214-5376-0.
Typ
Stať ve sborníku
Anotace
V článku je představena nová metoda pro návrh systémů maskujících jednu chybu, která kombinuje redundanci v ploše a v čase. Schopnost maskování chyb je srovnatelná s TMR. Navržená metoda je porovnána s TMR z hlediska plochy čipu a je identifikována skupina obvodů, pro které je její použití vhodné.

Novel C-Element Based Error Detection and Correction Method Combining Time and Area Redundancy

Rok
2015
Publikováno
Proceedings of the Euromicro Conference on Digital System Design - DSD 2015. Los Alamitos: IEEE Computer Society, 2015. p. 280-283. ISBN 978-1-4673-8035-5.
Typ
Stať ve sborníku
Anotace
In this work we present a novel fault-tolerant circuits design method. It combines time and area redundancy to achieve error-correction abilities similar to a triple-modular redundancy (TMR) and the area-overhead close to a duplex system. New logic gates design allowing a complete stuck-at fault testability will be presented. Our method allows to test combinational parts of the circuit using a universal short-duration offline test. The offline-testable module with an online-checker allows to compose a fault-tolerant system with the mentioned properties. This system will be denoted as a time-extended duplex scheme. In this scheme the offline test is sufficiently short to allow error correction during the computation (paused pipeline). The presented method adopts some principles from dual-rail logic and asynchronous circuits design.

Novel Error Detection and Correction Method Combining Time and Area Redundancy

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Rok
2015
Publikováno
Sborník příspěvků PAD 2015. Zlín: Universita Tomáše Bati ve Zlíně, 2015. pp. 48-53. ISBN 978-80-7454-522-1.
Typ
Stať ve sborníku
Anotace
In this paper, a novel fault-tolerant circuits design method is briefly described. It combines time and area redundancy to achieve error-correction abilities similar to triple-modular redundancy (TMR) and the area-overhead close to a duplex system. New logic gates design allowing complete stuck-at fault testability is presented.

Novel Gate Design Method for Short-Duration Test

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Rok
2015
Publikováno
Proceedings of the 19th International Scientific Student Conferenece POSTER 2015. Praha: Czech Technical University in Prague, 2015. ISBN 978-80-01-05499-4.
Typ
Stať ve sborníku
Anotace
In this paper, a novel logic gate design method will be presented. This method allows to test combinational parts of the circuit using a short-duration offline test. Short-duration offline tests are usable when fault-recovery in duplex-based systems is required and downtime should be minimized at the same time. The presented method adopts some principles from dual-rail logic and asynchronous circuits design.

Smart re-use of hardware peripherals for better software UART

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Rok
2015
Publikováno
Proceedings of the 3rd Prague Embedded Systems Workshop. Praha: ČVUT FIT, Katedra číslicového návrhu, 2015. pp. 17-23. ISBN 978-80-01-05776-6.
Typ
Stať ve sborníku
Anotace
In this work, the efficient software implementation of UART is presented. The efficiency is achieved by using the microcontroller peripherals intended for the different purpose.