Ing. Robert Hülle, Ph.D.

Publications

Evaluation of the Medium-sized Neural Network using Approximative Computations on Zynq FPGA

Year
2023
Published
Proceedings of 2023 12th Mediterranean Conference on Embedded Computing (MECO). Piscataway: IEEE, 2023. p. 1-4. ISSN 2637-9511. ISBN 979-8-3503-2291-0.
Type
Proceedings paper
Annotation
Integrating artificial intelligence technologies into embedded systems requires efficient implementation of neural networks in hardware. The paper presents a Zynq 7020 FPGA implementation and evaluation of a middle-sized dense neural network based on approximate computation by linearly approximated functions. Three famous benchmarks were used for classification accuracy evaluation and hardware testing. We use our highly pipelined neural hardware architecture that takes weights from block RAMs to save logic resources and enables their update from the processing system. The architecture reaches excellent design scalability, allowing us to estimate the number of neurons implemented in programmable logic based on single-neuron resources. We reached nearly full chip utilization while preserving the high clock frequency for the FPGA used.

Reducing Output Response Aliasing Using Boolean Optimization Techniques

Year
2023
Published
Proceedings of the 2023 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems. Piscataway: IEEE - Electron Devices Society, 2023. p. 33-38. ISSN 2473-2117. ISBN 979-8-3503-3277-3.
Type
Proceedings paper
Annotation
In digital circuit testing, output response compaction can have a significant impact on fault coverage. The loss of fault coverage is caused by aliasing in the output response compaction. Classical approaches to reducing (eliminating) fault aliasing are based on modifications of the compactor design or modifying precomputed test sequence. In this paper, we propose a completely different approach based on a dedicated test pattern generation algorithm. The algorithm generates a test sequence with minimal aliasing for targeted faults. As the generated test sequence is tailored to given static and dynamic compactor structures, any response compactor can be used without a change in the design. We expand on our previous work, zero-aliasing ATPG, and incorporate pseudo-Boolean optimization techniques in the process. The algorithm is evaluated using an LFSR-based MISR on a selection of benchmark circuits. A comparison with a state-of-the-art ATPG process without anti-aliasing measures is drawn.

Evaluation of the SEU Faults Coverage of a Simple Fault Model for Application-Oriented FPGA Testing

Year
2020
Published
Proceedings of the 23rd Euromicro Conference on Digital Systems Design. Los Alamitos, CA: IEEE Computer Soc., 2020. p. 684-691. ISBN 978-1-7281-9535-3.
Type
Proceedings paper
Annotation
Testing of FPGA-based designs persists to be a challenging task because of the complex FPGA architecture with heterogeneous components, and therefore a complicated fault model. The standard stuck-at fault model has been found insufficient. On the other hand, very precise FPGA fault models have been recently devised. However, these models are often excessively complex and require a lot of resources (run-time, memory) to manipulate with. In this paper, we propose a simple yet efficient combined fault model comprising bit-flips in look-up tables and stuck-at faults in the rest of logic. On~top of this model, a dedicated SAT-based application-oriented ATPG has been designed. The main contribution of this paper is the evaluation of efficiency of the fault model with the respective ATPG by exhaustive hardware emulation of all possible SEUs in the configuration memory that may influence the functionality of the circuit implemented in the FPGA. We show that the obtained fault coverage reaches up to more than 99%, which makes the method applicable in practice. Even though combinational circuits are assumed only, the method can be used to quickly test safety-critical combinational cores.

ZATPG: SAT-based Test Patterns Generator with Zero-Aliasing in Temporal Compaction

Year
2018
Published
Microprocessors and Microsystems. 2018, 2018(61), 43-57. ISSN 0141-9331.
Type
Article
Annotation
Aliasing in test response compaction is an important source of fault coverage loss. Methods to avoid the aliasing mostly require modification of the compactor to some extent. This can lead to a higher compactor complexity and consequently to higher area overhead, longer signal propagation delays, etc. In contrast to this standard approach, we propose a novel method, the Zero-aliasing ATPG (ZATPG), which is able to reduce the aliasing for any compactor used, thus without need of the compactor modification or redesign. This is achieved by constraining the test pattern generation process (ATPG), so that patterns exhibiting no aliasing are produced directly. Aliasing in both the spatial and temporal compactors is assumed. The method is based on modification of very basic SAT-based ATPG principles, thus any SAT-based ATPG can be used for its purpose. Also, the method is general enough to be applicable to any compactor design. We demonstrate our method on MISR compactors based on LFSR and cellular automata, using the single stuck-at fault model. Our method is able to find a test with zero aliasing and complete fault coverage for smaller compactors than a conventional, unguided ATPG. Thus, the area overhead of the compactor can be reduced, while the complete fault coverage is preserved.

SAT-based ATPG for Zero-Aliasing Compaction

Year
2017
Published
Proc. of the 20th Euromicro Conference on Digital System Design. Piscataway, NJ: IEEE, 2017. p. 307-314. ISBN 978-1-5386-2146-2.
Type
Proceedings paper
Annotation
Aliasing in the test response compaction is an important source of fault coverage loss. Methods to combat the aliasing generally require modification of the compactor to some extent. This can lead to a higher compactor complexity and consequently to higher area overhead, longer signal propagation delays, etc. We propose a novel method, the Zero-aliasing ATPG (ZATPG), which is able to reduce the aliasing without need of designing new compactors. ZATPG works by augmenting the SAT-based ATPG process to constrain test pattern generation to produce no aliasing in the compactor. The method is general enough to be applicable to any compactor design. We demonstrate our method on LFSR-based MISR compactors, using the Single Stuck-At fault model. Our method is able to find a test with zero-aliasing and complete fault coverage for smaller compactors than conventional, unguided ATPG. Thus, the area overhead of the compactor can be reduced, while the complete fault coverage is retained.

Test Patterns Generation with Zero-Aliasing

Year
2017
Published
Počítačové architektúry & diagnostika PAD 2017 - Zborník príspevkov. Bratislava: STU Scientific, 2017. pp. 35-38. ISBN 978-80-972784-0-3.
Type
Proceedings paper
Annotation
V tomto článku shrnuji své výsledky za 2. rok doktorského studia. Prezentuji automatický generátor testovacı́ch vektorů (ATPG), který je schopen vygenerovat test s nulovým maskovánı́m v daném libovolném kompaktoru: ZATPG. Disku- tuji silné a slabé stránky tohoto algoritmu, včetně námětů, jak jeho slabé stránky překonat. V závěru nastiňuji dalšı́ směřovánı́ výzkumu, které by mělo vést k disertačnı́ práci.

Generating Test for BIST

Year
2016
Published
Počítačové Architektury & Diagnostika PAD 2016 - Sborník příspěvků. Brno: Vysoké učení technické v Brně, 2016. ISBN 978-80-214-5376-0.
Type
Proceedings paper
Annotation
In this paper, I summarize results of my research in the 1st year of doctoral study, comparison of fault models for use in application-oriented FPGA testing, examination of properties of SAT instances encountered in an ATPG process. Additionally I present next possible research, generating test with zero aliasing.

SAT-ATPG for Application-Oriented FPGA Testing

Year
2016
Published
Proceedings of the 15th Biennial Baltic Electronics Conference. Tallin: Tallin University of Technology, 2016. p. 83-86. ISSN 1736-3705. ISBN 978-1-5090-1393-7.
Type
Proceedings paper
Annotation
In this paper we propose a SAT-based ATPG algorithm for application-oriented FPGA testing. For this purpose, a novel fault model is introduced which combines the stuck-at fault model for interconnects testing with the bit-flip model for LUT testing. The concept of SAT-based ATPG enables integrating these two models easily. Fault coverage and fault dominance of the two models is discussed in this paper, yielding suggestions for using the proposed combined model.