Ing. Stanislav Jeřábek

Ing. Stanislav Jeřábek

Ing. Jiří Buček, Ph.D.

Department of Computer Systems

This thesis describes improvements to existing FPGA smart-card emulator. Run-time configuration was implemented and foundation for ISO/IEC 14443- 4 based proprietary protocols support was laid out. To comply with these protocols requirements, hybrid approach with two components - FPGA and MCU - was used. Components are connected by SPI.

Thesis on DSpace

Ing. Stanislav Jeřábek

Ing. Michal Štepanovský, Ph.D.

Department of Digital Design

The bachelor's thesis is focused on the problematics of software emulation in the context of teaching the principles of computer architectures and associated hardware. There is a whole emulator development process presented in an example of a particular computer system, which is the Nintendo Entertainment System. The process consists of understanding the basic principles behind software emulation, analysis of the emulated system, design of the solution based on discovered information, and finally, the implementation of the emulator including testing. The goal of the implementation is to be as comprehensible as possible. The project also includes a universal platform for emulator development. To motivate other students (or hobbyists) interested in the topic, there is a list of possible extensions of the project in the last chapter of the thesis. Detailed documentation was created to make the project more accessible for emulator developers and potential project contributors.

Thesis on DSpace

Ing. Stanislav Jeřábek

Ing. Jiří Buček, Ph.D.

Department of Digital Design

This bachelor thesis is about solving the problem of using the produced energy by a photovoltaic power plant instead of distributing to electric power transmission. The aim of the thesis is to design a device that will control the consumption of energy produced using connected devices based on specified rules. During my work, I designed that monitors the current production of a photovoltaic power plant, household consumption and compares with the set rules. The appliance switches on if the production exceeds the consumption and the set rules are met. The attachment contains a block diagram and a description of the device connection.

Thesis on DSpace

Ing. Stanislav Jeřábek

Dr.-Ing. Martin Novotný

Department of Digital Design

Field Programmable Gate Arrays (FPGAs) have an ability of dynamic reconfiguration, which allows them to be reprogrammed at runtime by itself. One computation can be implemented in different ways at different times. An actual way at a specific time is not known for an attacker and therefore it is much more difficult to use side-channel leakage to gain sensitive information. This diploma thesis follows the paper [1], which describes usage of three different countermeasures on PRESENT encryption algorithm. In this thesis, all these countermeasures were applied to PRESENT, SERPENT and AES. AES algorithm was implemented in two ways. The first way is based on the approach described in [1]. The second way uses a composite finite field to implement S-Box and therefore needs less CFGLUTs.

Thesis on DSpace