Yield & Robustness in Today’s Advanced Technology Nodes

Lecturer:   Yervant Zorian (Fellow & Chief Architect, Synopsys)
Date and time: 18th March 2016, 11:00 a.m.
Place:       lecture room T9:155, FIT CTU in Prague, 9 Thákurova Street
Language: English

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With the wide adoption of nanometer technologies, it has become crucial for today’s SOCs to use advanced yield and robustness optimization solutions. These solutions provide comprehensive detection and repair of not only random defects, but also systematic and process variation defects often manifested under unique test corners. Moreover, with the adoption of FinFET technologies, these advanced solutions are extended to cover new FinFET specific defects. This keynote, besides discussing the key trends and challenges of advanced nanometer technologies, will cover solutions to handle the wide range of potential defectivity in today’s SOCs. It will also address post-silicon analysis and yield optimization trade-offs using volume diagnostic, failure coordinate calculation, reconfiguration and repair. With the proliferation of high-density packaging, such as 2.5D and 3D-ICs, this keynote will also cover robustness of dies and interconnects, via advanced test solutions based on IEEE test access standards. 

Admission is free of charge.
The lecture was co-organized IEEE SB na ČVUT.

Last modified: 14.1.2019, 14:23