Digital Design & Dependability Research Group

DDD group conducts basic research in the area of digital design, mainly in the area of digital design methodologies with respect to optimizations of many parameters: area overhead, working frequency, low-power, latency, testability, dependability, fault – tolerance, attack resistance. Also, it focuses on hardware-software codesign and design of cryptographic hardware. The results of the basic research are verified using practical experiments and projects performed in labs equipped with programmable hardware kits (FPGA) and processors and EDA tools. The DDD group is also active in organizing international conferences (Euromicro DSD, DDECS). In 2013, it started The Prague Embedded Systems Workshop series.  


  • Arithmetic circuits for cryptography
  • Asynchronous circuits design
  • Attack resistant systems
  • Cryptanalysis by massively parallel FPGA engines
  • Formal verification of hybrid circuits
  • Hardware implementation of specific algorithms
  • Logic synthesis and optimization
  • Reliability, dependability, and testing of logic circuits
  • SEU-resistant systems in FPGA




7AMB14SK177 (Ministry of Education, Youth and Sports): Verification and dependability of digital systems design, main investigator: doc Ing. Hana Kubátová, CSc., 01/2014-12/2015.

FIŠER, P., SCHMIDT, J., and BALCÁREK, J.: Sources of Bias in EDA Tools and Its Influence. In: Proceedings of the 2014 IEEE 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, IEEE, 2014, pp. 258-261. ISBN 978-1-4799-4560-3.
LEMBERSKI, I. and FIŠER, P.: Dual-Rail Asynchronous Logic Multi-Level Implementation. Integration, the VLSI Journal, 2014, 47(1), 148-159. ISSN 0167-9260.
VÍT, P., BORECKÝ, J., KOHLÍK, M., and KUBÁTOVÁ, H.: Fault Tolerant Duplex System with High Availability for Practical Applications. In: Proceedings of 2014 17th Euromicro Conference, IEEE, 2014, pp. 320-325. ISBN 978-1-4799-5793-4.

BALCÁREK, J., FIŠER, P., and SCHMIDT, J.: Techniques for SAT-Based Constrained Test Pattern Generation. Microprocessors and Microsystems, 2013, 37(2), 185-195. ISSN 0141-9331.
KYNCL, J., HARIRAM, A., and NOVOTNÝ, M.: On Measurement of Synchronous Phasors in Electrical Grids. In: ISCAS 2013 Conference Proceedings, IEEE, 2013, pp. 2972-2975. ISBN 978-1-4673-5760-9.
SCHMIDT, J., FIŠER, P., and BALCÁREK, J.: The influence of implementation type on dependability parameters. Microprocessors and Microsystems, 2013, 37(6-7), 641-648. ISSN 0141-9331.
BUČEK, J., KUBALÍK, P., LÓRENCZ, R., and ZAHRADNICKÝ, T.: Dedicated Hardware Implementation of a Linear Congruence Solver in FPGA. In: The 19th IEEE International Conference on Electronics, Circuits, and Systems, IEEE, 2012, pp. 689-692. ISBN 978-1-4673-1261-5.
BORECKÝ, J., KOHLÍK, M., KUBALÍK, P., and KUBÁTOVÁ, H.: Fault Models Usability Study for On-line Tested FPGA. In: Proceedings of the 14th Euromicro Conference on Digital System Design, IEEE, 2011, pp. 287-290. ISBN 978-0-7695-4494-6.
KUBÁTOVÁ, H. and KUBALÍK, P.: Fault-tolerant and fail-safe design based on reconfiguration. In: Design and Test Technology for Dependable Systems-on-Chip, IGI Global, 2011, pp. 175-194. ISBN 978-1-60960-212-3.
GUENEYSU, T., KASPER, T., NOVOTNÝ, M., PAAR, C., and RUPP, A.: Cryptanalysis with COPACOBANA. IEEE Transactions on Computers, 2008, 57(11), 1498-1513. ISSN 0018-9340.

Doc. Ing. Hana Kubátová, CSc.


Last modified: 22.1.2019, 15:32