Ing. Jan Bělohoubek, Ph.D.

Article

10.1016/j.microrel.2021.114281

Department of Digital Design
Department of Information Security

Physical attacks, namely invasive, observation, and combined, represent a great challenge for today's digital design. Successful class of strategies adopted by industry, allowing hiding data dependency of the side channel emissions in CMOS is based on balancing. Although attacks on CMOS dynamic power represent a class of state-of-the-art attacks, vulnerabilities exploiting data dependency in CMOS static power and light-modulated static power were recently presented. In this paper, we describe structures and techniques developed to enhance and balance the power imprint of the traditional static CMOS bulk structures under invasive light attack. The novel standard cells designed according to the presented techniques in the TSMC180nm technology node were used to synthesize the dual-rail AES SBOX block. The behavior of the AES SBOX block composed of the novel cells is compared to classical approaches. Usage of novel cells enhances circuit security under invasive light attack while preserving comparable circuit resistance against state-of-the-art power attacks.

Proceedings paper

10.1109/DDECS50862.2020.9095656

Department of Digital Design

Physical attacks, namely invasive, observation and combined, represent a great challenge for today’s digital design. Successful class of strategies adopted by industry, allowing hiding data dependency of the side channel emissions in CMOS is based on balancing. Although attacks on CMOS dynamic power represent a class of state-of-the-art attacks, vulnerabilities exploiting data dependency in CMOS static power and light- modulated static power were recently presented. In this paper, we describe structures and techniques developed to enhance and balance traditional static CMOS bulk structures. To enable data dependency hiding, we propose low-level techniques based on complementary-value induced balancing currents, constant current source behavioral approximation, and light-sensing capability of traditional CMOS structures. The proposed techniques may be used to build a dual-rail circuit balanced from both perspectives: static and dynamic power. The publicly available TSMC180nm node standard cell simulation is used for evaluation.

Proceedings paper

10.1109/DSD.2019.00062

Department of Digital Design

As digital devices penetrate to many areas important for the present society, it is important to analyze even potential threats to mitigate vulnerabilities during their lifetime. In this paper, we analyze the data dependency of the photocurrent induced by a laser beam in the illuminated CMOS circuit. The data dependency may introduce potential threat(s) originating in the nature of the CMOS technology. The data dependency can be potentially misused to compromise the data processed by an embedded device. We show that also the devices employing dual-rail encoding to hide data-dependency are not safe.

Proceedings paper

10.1109/DDECS.2019.8724663

Department of Digital Design

The security of many digital devices strongly depends on a secret value stored in them. To mitigate security threats, high protection of such a value must be provided. Many attacks against (cryptographic) hardware as well as attack countermeasures were presented recently. As new attacks are invented continuously, it is important to analyze even potential threats to mitigate device vulnerability during its lifetime. In this paper, we report a novel voter-related vulnerability, which can be potentially misused to compromise the secret value stored in an embedded device.

Proceedings paper

Department of Digital Design

Spolehlivost a bezpečnost jsou důležité vlastnosti vyžadované od mnoha zařízení. Zvýšení spolehlivosti a bezpečnosti systému lze dosáhnout mimo jiné vhodnou mikroarchitekturou. Dokončený výzkum se věnoval právě zvyšování spolehlivosti číslicových systémů na úrovni mikroarchitektury. Výzkum na něj bezprostředně navazující cílí na řešení spojující přístupy zajišťující zároveň bezpečnost i spolehlivost dílčích částí číslicových systémů. Velká část příspěvku je věnována rešerši, jež se váže k navrhovanému konceptu uTMR.

Article

10.1016/j.micpro.2017.06.007

Department of Digital Design

The method proposed in this article allows to construct error-masking fail-operational systems by com- bining time and area redundancy. In such a system, error detection is performed online, while error masking is achieved by a short-duration offline test. The time penalty caused by the offline test applies only when an error is detected. The error-masking ability in such a system is very close to TMR, the area overhead is smaller for a well defined class of circuits, and the delay penalty caused by the offline test remains reasonably small. The short-duration offline test is possible only when extensive design-for-test practices are used. Therefore, a novel gate structure is presented, which allows to construct combina- tional circuits testable by a short-duration offline test. The proposed test offers com plete fault coverage with respect to the stuck-on and stuck-open fault model. The proposed solutions are combined and a comprehensive description of the overall error-masking architecture is provided.

Proceedings paper

10.1109/DSD.2016.62

Department of Digital Design

The method proposed in this paper allows to construct error-correcting systems by combining time and area redundancy. In such a system, error detection is performed online, while error correction uses a short-duration offline test. The time penalty caused by the offline test applies only when an error is detected. The error-correcting ability in such a system is comparable with TMR, the area overhead is smaller for a class of circuits, and the delay penalty caused by the offline test remains reasonably small. The short-duration offline test is possible only when extensive design-for-test practices are used. Therefore, a novel gate structure is presented, which allows to construct combinational circuits testable by a short-duration offline test. The proposed test offers complete fault coverage with respect to the stuck-on and stuck-open fault model.

Proceedings paper

Department of Digital Design

V článku je představena nová metoda pro návrh systémů maskujících jednu chybu, která kombinuje redundanci v ploše a v čase. Schopnost maskování chyb je srovnatelná s TMR. Navržená metoda je porovnána s TMR z hlediska plochy čipu a je identifikována skupina obvodů, pro které je její použití vhodné.

Proceedings paper

10.1109/DSD.2015.95

Department of Digital Design

In this work we present a novel fault-tolerant circuits design method. It combines time and area redundancy to achieve error-correction abilities similar to a triple-modular redundancy (TMR) and the area-overhead close to a duplex system. New logic gates design allowing a complete stuck-at fault testability will be presented. Our method allows to test combinational parts of the circuit using a universal short-duration offline test. The offline-testable module with an online-checker allows to compose a fault-tolerant system with the mentioned properties. This system will be denoted as a time-extended duplex scheme. In this scheme the offline test is sufficiently short to allow error correction during the computation (paused pipeline). The presented method adopts some principles from dual-rail logic and asynchronous circuits design.

Proceedings paper

Department of Digital Design

In this paper, a novel fault-tolerant circuits design method is briefly described. It combines time and area redundancy to achieve error-correction abilities similar to triple-modular redundancy (TMR) and the area-overhead close to a duplex system. New logic gates design allowing complete stuck-at fault testability is presented.

Proceedings paper

Department of Digital Design

In this paper, a novel logic gate design method will be presented. This method allows to test combinational parts of the circuit using a short-duration offline test. Short-duration offline tests are usable when fault-recovery in duplex-based systems is required and downtime should be minimized at the same time. The presented method adopts some principles from dual-rail logic and asynchronous circuits design.

Proceedings paper

Department of Digital Design

In this work, the efficient software implementation of UART is presented. The efficiency is achieved by using the microcontroller peripherals intended for the different purpose.