Ing. Filip Kodýtek, Ph.D.

Theses

Bachelor theses

TRNG implementation on ARM Cortex-M0

Author
Tomáš Zach
Year
2018
Type
Bachelor thesis
Supervisor
Ing. Filip Kodýtek
Reviewers
prof. Ing. Róbert Lórencz, CSc.
Summary
This work deals with true random number generators (TRNG). At first, a literature research concerning TRNG with a focus on microcontrollers is done. Then own implementation of TRNG using microcontroller with ARM-CORTEX-M0 processor is introduced. Finally measurements of the proposed design are evaluated with a set of statistical tests.

Implementation of SRAM-based TRNG on a microcontroller

Author
Daniel Jantošovič
Year
2022
Type
Bachelor thesis
Supervisor
Ing. Filip Kodýtek, Ph.D.
Reviewers
Ing. Jiří Buček, Ph.D.
Summary
This bachelor thesis deals with random number generators. At the beginning, it deals with their classification in terms of determinism or design principles and gives examples of usability in practice. Subsequently, it delves deeper into the generators of true random numbers implemented on microcontrollers. The following is the design and implementation of a random number generator with the power-up state of the static RAM cells as the source of its entropy on a microcontroller with a processor of ARM Cortex-M4 architecture. Finally, the implemented generator is subjected to a statistical tests

Implementation and analysis of TERO-based TRNG on FPGA

Author
Tomáš Suda
Year
2025
Type
Bachelor thesis
Supervisor
Ing. Filip Kodýtek, Ph.D.
Reviewers
prof. Ing. Róbert Lórencz, CSc.
Summary
The work focuses on true random number generators (TRNGs), namely the TERO variant, a temporarily oscillating ring oscillator. First, the work introduces general concepts, other common number generators, or evaluation methods. Then, the TERO core is described in detail, and one possible approach is realized on an Arty A7 FPGA. The implementation is thoroughly analyzed using multiple methods, including analog signal capture or statistical evaluation of the circuit properties and the oscillations. The evaluated data show interesting properties that should be met by the design to allow good entropy and, consequently, the overall security of the whole system. The throughput of the design can be greater than 1 Mbit/s. The practical part of the work can serve as a robust platform for future research.