Ing. Martin Kohlík, Ph.D.

2025 - 2027

The ACDRC Embedded AI Processor for Automotive Applications project aims to intelligent driving technologies enhance driving safety through sensing, analysis, and decision-making. Central to these technologies is the ability to perceive the surrounding environment using sensors, which collect data and process it using embedded AI processors. These processors provide efficient AI computation, critical for intelligent driving systems machine learning (ML) and artificial intelligence (AI) techniques. Current embedded AI processors are often designed for general purposes, which may not meet the stringent requirements of automotive applications, such as low power consumption, high efficiency, and high performance. The specific needs of automotive intelligent driving applications demand optimized solutions. This project aims to develop an FPGA-based embedded AI processor optimized for specific automotive intelligent driving applications. The processor will handle 1Mp30 image signals, outputting detected object boundary coordinates and object categories.

2010

Project will be focused on dependable system design implemented in programmable gate arrays (FPGA) and their testing. Increasing of dependability of circuits will be achieved by effective usage of dynamic reconfiguration. For improving the testability of the circuits a method for decomposition of the circuit will be developed. The compressed test generation methodology based on overlapping of the test vectors will be improved using their implicit representation to maximize the test effectivity. We will also focus on circuit's area with goal to minimize the hardware overhead. Developed architecture and methods will be tested on experimental designs in FPGA.

2012

This project is focused on digital system´s design with respect to their hardware area, working frequency, power, realiability issues and testability. Pilot implementations will realized in FPGA. Hign realiability parameters will be achieved by dynamical re-configuration. The compressed test generation methodology based on overlapping of the test vectors will be improved using their implicit representation to maximize the test effectivity.

2011

The research projects of Digital Design and Dependability group are focused on dependable system design implemented in programmable gate arrays (FPGA) and their testing. Increasing of dependability of circuits will be achieved by effective usage of dynamic reconfiguration. For improving the testability of the circuits a method for decomposition of the circuit will be developed. Dependability models are the necessary part of such research, because they allow us to verify dependability parameters improvements gained from developed methods. The main features of dependability models will be simplicity, easy extension and easy modification. The models will be used to calculate dependability parameters in industrial applications such as railway security systems.