Ing. Martin Kohlík, Ph.D.

Theses

Bachelor theses

Analysis of the possibilities of user functions and libraries in Mathematica

Author
Jan Řezníček
Year
2017
Type
Bachelor thesis
Supervisor
Ing. Martin Kohlík, Ph.D.
Reviewers
Ing. Martin Daňhel, Ph.D.
Summary
The main topic of the Bachelor Thesis is a guide to create library for computing in Wolfram Mathematica and sample of work with created library for computing of dependability models baased on Markov chains.

Master theses

Advanced simulation methods in SystemVerilog

Author
Miroslav Kallus
Year
2021
Type
Master thesis
Supervisor
Ing. Martin Kohlík, Ph.D.
Reviewers
Ing. Jaroslav Borecký, Ph.D.
Summary
This thesis deals with digital circuit simulation tools. In research part I am going to learn basic constructs of SystemVerilog language and UVM library. Then, I am going to test testbench design tools, like text editors and IDEs, and simulation tools. In the end, I'll create helpful text for using SystemVerilog and the UVM library including examples of source code. There will also be model projects for the Digital Circuit Simulation course.

Outdoor activities support device

Author
Tomáš Čermák
Year
2019
Type
Master thesis
Supervisor
Ing. Martin Kohlík, Ph.D.
Reviewers
Ing. Filip Štěpánek
Summary
This diploma thesis deals with the creation of a system that allows playing the bomb defusal mode from the computer game Counter-Strike for airsoft and paintball players. The system consists of a stations and a handheld device. The handheld device mimics a bomb. The station indicates and area where handheld device can be set up and countdown get started. A development board containing ESP32 microcontroller was used to create both devices. Both devices include a buzzer for a sound effects and an led diode. The handheld device also includes a keyboard and a display. The devices are programmed using the Arduino platform. The design and implementation result in a real prototype of this system. Source codes and 3D models of the protective covers prepared for a 3D print can be found in the attachment.

CPU simulation in SystemVerilog

Author
Vojtěch Jílek
Year
2022
Type
Master thesis
Supervisor
Ing. Martin Kohlík, Ph.D.
Reviewers
Ing. Jiří Kašpar
Summary
This thesis deals with design of simulation environments for processor simulation in the SystemVerilog language. The UVM library, its register model and the QuestaSim development environment are used to simulate processors. In this work, a simulation environment for two processors is designed - a singlecycle processor and a pipeline processor. Part of this thesis is a brief text with a description of several problems that a novice developer may encounter when using the registry model of the UVM library.

Nonhomogeneous dependability models calculations

Author
Jan Řezníček
Year
2019
Type
Master thesis
Supervisor
Ing. Martin Kohlík, Ph.D.
Reviewers
Ing. Martin Daňhel, Ph.D.
Summary
This diploma thesis deals with describing the calculation method of reliability and distribution function of Markov Chains with nonhomogeneous parameters. Implementation is programmed in Wolfram Mathematica. The method can be used to perform calculations on several types of distributions (not only the exponential one) due to its ability to model nonhomogeneous systems. The method is tested and compared with existing methods with respect to time and accuracy. This testing was focused on the impact of input parameters and comparison with homogeneous Markov Chains. The work also describes the contribution of this method from the perspective of reliability calculations and the possibility of the future work.