Ing. Pavel Kubalík, Ph.D.

Projects

Design of Error Detection Methods with Instantly Correction for Critical Applications in FPGA

Program
Studentská grantová soutěž ČVUT
Code
SGS11/090/OHK3/1T/18
Period
2011
Description
This project will be focused on dependable circuits design implemented in programmable gate arrays(FPGA). These circuits will be composed from smaller secured blocks. Increasing of dependability of circuits will be achieved via their reconfiguration and via a method for decomposition of the circuits. Newly created smaller blocks will be secured effectively. We will also focus on circuit's area with the goal to minimize the hardware overhead. All methods will be applied on the set of benchmarks and on five blocks of the safety railway station system. Final dependable circuits will be tested in FPGA.

Digital design methods and procedures and their experimental verification

Program
Studentská grantová soutěž ČVUT
Code
SGS12/094/OHK3/1T/18
Period
2012
Description
This project is focused on digital system´s design with respect to their hardware area, working frequency, power, realiability issues and testability. Pilot implementations will realized in FPGA. Hign realiability parameters will be achieved by dynamical re-configuration. The compressed test generation methodology based on overlapping of the test vectors will be improved using their implicit representation to maximize the test effectivity.

Study of properties of residual arithmetic for solving sets of linear equations

Program
Standard projects
Provider
Czech Science Foundation
Code
GAP103/12/2377
Period
2012 - 2014
Description
Our intention is to study the properties of the multiple-modulus residual arithmetic with respect to specific numerical problems of linear algebra. One of complex problems of linear algebra suitable for our purpose is solving large systems of linear equations. This requires to create a model of a solver for performing experiments. The method of Gauss-Jordan elimination with residual pivoting is chosen as the base of the solver. In order to gain precise knowledge about the arithmetic used in the model, a hardware architecture of the model will be emulated on FPGA. This experimental solution enables us also verify the theoretical prediction about the spatial, temporal and communication complexity of the modeled solver.