Digital design methodology
Program
Studentská grantová soutěž ČVUT
Provider
Czech Technical University in Prague
Departments
Investigators
Period
2013
Description
This project is focused on digital system´s design with respect to their hardware area, working frequency, power, realiability issues and testability. Pilot implementations will realized in FPGA. Hign realiability parameters will be achieved by dynamical re-configuration. The test generation methodology will be improved.