Theses

Ing. Tomáš Novák

Dr.-Ing. Martin Novotný

Department of Digital Design

This diploma thesis covers the RTL design and implementation of System On Chip based on the RISC-V processor platform for USI graphical pen controller. The current CoolRISC-based pen controller SoC is analysed and based on this analysis new system design for the RISC-V-based pen controller SoC is created. The RTL design of the new SoC is implemented into 180\,nm technology, and its system power consumption is measured in simulation and then compared to the existing CoolRISC-based system. The thesis also covers the technical comparison between CoolRISC and RISC-V processor platforms.

Thesis on DSpace

Ing. Martin Daňhel, Ph.D.

Ing. Roman Knížek

Department of Digital Design

This master's thesis provides a comprehensive analysis of the Robot Operating System (ROS) 2, including its architecture, communication patterns, concepts, and use of the Data Distribution Service (DDS) as a middleware for data sharing. Additionally, the thesis explores Micro-ROS, a lightweight version of ROS 2 designed to run on microcontrollers with limited resources. This work focuses on analyzing the Micro-ROS's architecture, features, and suitability for embedded systems use. Additionally, the thesis explores using PXROS-HR, a real-time operating system (RTOS), in the proposed solution. The proposed solution involves building a custom static library for Micro-ROS and implementing a mutex task for thread-safe data access. The project structure is presented, including configurations and linker files, and describes the implementation of custom allocators and custom transport for Micro-ROS. The thesis also includes demonstrations of multithread publisher-subscriber and multicore publisher-subscriber for Micro-ROS, showcasing the proposed solution's feasibility and effectiveness. Furthermore, the proposed solution is evaluated by conducting one test for each demo, including publishing and subscribing to a topic, creating a service server for remote procedures, and distributing work to multiple tasks or cores. The results demonstrate that the proposed solution achieves thread-safe data access and enables efficient communication in resource-constrained environments.

Thesis on DSpace

Ing. Jiří Andrle

Dr.-Ing. Martin Novotný

Department of Digital Design

This work describes the implementation of a device that aims to guard a defined area inside a car against the intrusion of unwanted objects. The protected area is covered with direct Time-of-Flight (dToF) sensors from STMicroelectronics, which are qualified for automotive applications. The device has been designed from the ground up to be a self-contained unit that includes not only the protected area itself but also all the electronics needed to read the sensor data and evaluate the presence of objects. The basic detection algorithm has been implemented on a PowerPC microcontroller and its results are signaled in real time by an LED. All integrated circuits and other electrical components were soldered on custom PCBs designed specifically for this thesis. The device can optionally be connected via USB cable to a desktop user interface that can graphically represent the sensor data, but in addition, it also allowed for easier development of a more advanced version of the detection algorithm. This external variant was also used for final testing, which showed that the system could correctly respond to the presence of most spatially significant objects, but for example a coin and other objects with low reflectivity could not be reliably detected over the entire protected area. Several external factors were also discovered that further negatively affect the algorithm and should be taken into account in future versions.

Thesis on DSpace

Ing. Martin Kohlík, Ph.D.

Ing. Jiří Kašpar

Department of Digital Design

This thesis deals with design of simulation environments for processor simulation in the SystemVerilog language. The UVM library, its register model and the QuestaSim development environment are used to simulate processors. In this work, a simulation environment for two processors is designed - a singlecycle processor and a pipeline processor. Part of this thesis is a brief text with a description of several problems that a novice developer may encounter when using the registry model of the UVM library.

Thesis on DSpace

Ing. Miroslav Skrbek, Ph.D.

doc. Ing. Ivan Šimeček, Ph.D.

Department of Digital Design

This thesis deals with controlling the autonomous vehicle, based on microcomputer Raspberry Pi. This vehicle model was improved with sensors for measuring distance and with incremental encoders for measuring travelled distance, speed and direction. Additionally, the vehicle was improved with more parts for improved driving properties and simplifying the use of the model. For sensor connections printed circuit boards were created. The car's control software was also modified. A~complex autonomous driving system was created for the model, which included a track with road signs, ultrasound car localisation and an application for track recognition. Recognition is performed both in a traditional way (openCV) and with the use of neural networks. The driving system and the modified model were tested on different model tracks.

Thesis on DSpace

Ing. Filip Štěpánek

Ing. Martin Kohlík, Ph.D.

Department of Digital Design

Datalogger is a device that records data over time. The content of this thesis discusses how to appropriately design and implement a homemade datalogger suitable for measuring the spectrum of ionizing radiation. Within the assignment, the requirements for functionality and technical equipment / design of the product are discussed. The realisation consists of designing of a printed circuit board, embedded firmware for the STM32 microcontroller and the Wi-Fi module ESP-01. It also includes implementation of the service PC application for Windows 10. Physical background of the measurement of the ionizing radiation spectrum as well as details regarding the design, realization, and testing of the final product are described in the text.

Thesis on DSpace

Dr.-Ing. Martin Novotný

Ing. Jakub Klemsa

Department of Digital Design

With the rise of cloud compute services, the privacy of user's data is often put into question, as the service provider has full access to it. This is further exacerbated by facilities that hold private data, but lack the computational power to run their own research - namely hospitals. A Fully Homomorphic Encryption (FHE) could be a solution to this problem as it can evaluate arbitrary functions over encrypted data without the need for decryption on the Cloud service provider's side. Since the breakthrough by Gentry et al. in 2009, this field is very active with Chilloti et al. recently introducing the scheme called TFHE. TFHE scheme has been shown to be suitable for securing Machine Learning as a Service (MLaaS). TFHE in its original form only works with one-bit plaintext space, however, several improvements allow the usage of multivalue plaintext space. This improved version was codenamed netWork-ready TFHE (WTHE). In general, (W)TFHE Schemes implemented in software are several orders of magnitude slower than the commonly used encryption schemes. This thesis serves as a case study to determine the feasibility of accelerating the WTFHE Scheme with an FPGA. Our contributions consist of designing an FPGA accelerator capable of simple Neural Network evaluation, measuring its performance compared to the software setup, discovering resource requirements, and the potential of scalability.

Thesis on DSpace

Ing. Jakub Novák

Dr.-Ing. Martin Novotný

Department of Digital Design

The aim of the work is to create a hardware system to focus the view of industrial camera in the sense of getting higher resolution in area of interest. A solution to use two cameras was chosen. The first one is an overview camera and the second one is a detail camera, which gaze is aimed by a mirror tilted in two axis. The created solution enables to aim to a wanted object from an overview camera and retrieve its detail in higher resolution by the detail camera. The main result of the work is the created hardware system and its firmware to control tilting of the mirror.

Thesis on DSpace

Ing. Jiří Hušák

Ing. Robert Hülle, Ph.D.

Department of Digital Design

This thesis includes the design and implementation of a flash memory bootloader for a RISC-V microcontroller. Communication is done over the NFC board NTAG5 link. Design and implementation of the communication are also present in this thesis. The created bootloader is robust, and its memory footprint is small. As a part of this thesis, an Android application was created to test the bootloader.

Thesis on DSpace

Ing. Martin Daňhel, Ph.D.

Ing. Tomáš Zimmerhakl

Department of Digital Design

This diploma thesis deals with automated testing of the infotainment unit of a car. The thesis provides theoretical information about the scripting language TCL and the CAN bus, which are the basis for creating automated tests. Introduction to the process of developing a graphical interface is accompanied by motivation for improvement. Based on the introduced motivation, the principle and involvement of automated testing in the development process of the graphical interface is designed. The thesis contains the documentation of the test rack, which is performed in terms of used hardware and software. The TCL language is used to create test functions and test cases to detect errors of the grafical interface. This thesis describes the whole testing process with the report of results.

Thesis on DSpace

doc. Dipl.-Ing. Dr. techn. Stefan Ratschan

doc. Ing. Jan Schmidt, Ph.D.

Department of Digital Design

In this thesis, a new utility is presented for performing formal deadline checking of simple microcontroller programs at machine code level. The existing formal verification approaches and tools are studied and their weaknesses identified. Namely, source level techniques cannot guarantee cycle-count precise execution times, while machine code verification tools are few, not generally available, and usually heavily tailored to a specific processor, significantly reducing their usefulness. To counteract the weaknesses of current microcontroller verification tools, a novel hybrid approach is proposed and implemented. Machine code level model checking techniques are used for state space representation and verification of adherence to specification. Microcontroller memory and step behaviour is specified using a simple imperative language that can be manipulated using standard source code level techniques. This allows cycle-count based deadline checking, simple extension to other microcontrollers in addition to the implemented ATmega328P, and implementation of advanced techniques without dependence on the actual processor used. In addition to the core functionality, advanced techniques for handling nondeterminism, control flow generation, and simple cycle path reduction are implemented. The utility is tested, showing its usefulness for simple program deadline verification. The impact of various techniques used is discussed and promising future improvements are identified.

Thesis on DSpace

Ing. Pavel Kubalík, Ph.D.

Ing. Vojtěch Miškovský, Ph.D.

Department of Digital Design

This diploma thesis is centered around the design and realization of a surveillance device for the internet of things (IoT), which utilizes the GSM network using embedded systems. The created surveillance device sends taken photos to a remote server via the existing cellular network with a common SIM card. The surveillance device consists of four main components: driving Arduino, SD card adapter, camera and GSM module. Measuring this IoT device when it is performing various tasks is an integral part of the work. A second Arduino was used for measuring. Power consumption, throughput and latency were measured. Measurement methodology of acquiring individual measured values is described in detail and findings regarding the usability of this device in IoT are shown. Battery lifespan for this device is also discussed. The usability of LTE speeds for the given device is explored and a speedup ratio for sending files while using this speed is calculated.

Thesis on DSpace

Ing. Jakub Klemsa

Dr.-Ing. Martin Novotný

Department of Digital Design

Homomorphic encryption is an effective way of securing data privacy while maintaining the possibility to process the data. The VeraGreg framework, unlike other existing homomorphic cryptosystem allows for verification of computation that was done with the encrypted data. This work deals with an implementation of the VeraGreg framework and its effectiveness comparison with a na¨ive scheme based on symmetric encryption. Secure microcontroller CE1302 was chosen as the implementation platform. A new library for multiprecision integer arithmetic was created as well as the first published implementation of Paillier cryptosystem using hardware RSA accelerator. The VeraGreg framework is 200 times slower compared to the naive scheme and occupies one third more space in the program memory, so it is not a suitable alternative to symmetric cryptosystems. On the other hand, it provides privacy to the user while allowing computations with the encrypted data, and verifying that is has not been manipulated during the computation.

Thesis on DSpace

Ing. Stanislav Jeřábek

Dr.-Ing. Martin Novotný

Department of Digital Design

Field Programmable Gate Arrays (FPGAs) have an ability of dynamic reconfiguration, which allows them to be reprogrammed at runtime by itself. One computation can be implemented in different ways at different times. An actual way at a specific time is not known for an attacker and therefore it is much more difficult to use side-channel leakage to gain sensitive information. This diploma thesis follows the paper [1], which describes usage of three different countermeasures on PRESENT encryption algorithm. In this thesis, all these countermeasures were applied to PRESENT, SERPENT and AES. AES algorithm was implemented in two ways. The first way is based on the approach described in [1]. The second way uses a composite finite field to implement S-Box and therefore needs less CFGLUTs.

Thesis on DSpace

Ing. Vojtěch Miškovský, Ph.D.

Dr.-Ing. Martin Novotný

Department of Digital Design

Side-channel cryptanalysis pose a serious threat to many modern cryptographic systems. Typical side-channel attack consists of an active phase, where data are acquired, and an analytical phase, where the data get examined and evaluated. A software toolkit is presented in this thesis, which includes support for cryptographic device control, oscilloscope data acquisition, data preprocessing, statistical analysis and evaluation of the attack. The toolkit is composed of non-interactive text-based utilities with a modular plug-in architecture, and it is released under open-source licence.

Thesis on DSpace

doc. Dipl.-Ing. Dr. techn. Stefan Ratschan

doc. RNDr. Pavel Surynek, Ph.D.

Department of Digital Design

Many nowadays systems, namely embedded, are insisted to satisfy high specification requirements, which often depend on physical features of real world. Formal verification showed to be convenient method to guarantee specifications fulfillment in complex systems. Formal verification checks mathematical model of a system exactly; one of used approaches is e.g. SAT. Problem arises when one needs to use another means of modelling--differential equations (ODEs), which describe physical features natively. Goal of this paper is to prove a concept which combines SAT with ODEs and can be used e.g. to formally verify models of embedded systems. Such solvers already exist (e.g. dReal), but their usage in industry is limited due to their preference of accuracy over speed in ODEs. The objective was to apply classic numerical methods for solving ODEs, which are less accurate, but faster. This work includes prototype implementation named SOS (SMT+ODE Solver), which combines SMT (extension of SAT) with ODEs. SMT and ODE solvers are both independent of rest components. Used solvers are odeint and from SMT solvers CVC4 and z3. The major observations are that using classic numerical methods fastens overall computation, and that computation time of tasks with precise initial values (IVP) is much smaller than at tasks with intervals (IIVP). And intervals can be effectively approximated by value enumerations in logical sum. These observations approve our chosen concept and were verified in some examples, where our procedure was faster than in current solver dReal. Thus the goal of a more appropriate method for industry needs, in the field of formal verification with ODEs, has been reached. This work is assumed to serve as a source of inspiration to industry tools' designers. Or, it can be developing and improving henceforth inside the current open-source project.

Thesis on DSpace

doc. Ing. Jiří Douša, CSc.

Department of Digital Design

This Master's thesis is focused on smart sensor verification environment implementation. A smart sensor, according to generally accepted industry definitions, combines a sensing element, an analog-to-digital converter (ADC), and a bus interface. The work of this thesis was divided into three tasks. The first task was to study literature to get to know basics of modern verification approaches. The second task was to design and build a smart sensor model, which would serve as design under test for the testbench verification. The third task was to implement and verify the testbench. The main output of this thesis is a testbench suitable for smart sensor verification, implemented using Unified Verification Methodology (UVM) and SystemVerilog. The testbench has been verified in simulator and coverage metrics have been collected during simulation to track the progress of verification.

Thesis on DSpace

Ing. Pavel Kubalík, Ph.D.

doc. Ing. Alois Pluháček, CSc.

Department of Digital Design

This work aims to create cross-platform application for simulating microprogrammed processor DOP used for educational purpose. Using this application students should be able to understand principals of microprogrammed processors and implement their own instruction to DOP instruction set.

Thesis on DSpace

Dr.-Ing. Martin Novotný

Ing. Tomáš Vaňát, Ph.D.

Department of Digital Design

doc. Ing. Jan Schmidt, Ph.D.

Ing. Stanislav Trojan

Department of Digital Design