Performance Comparison of Multiple Approaches of Status Register for Medium Density Memory Suitable for Implementation of a Lossless Compression Dictionary
Authors
Bartík, M.; Ubik, S.; Kubalík, P.; Beneš, T.
Year
2018
Published
Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays. New York: ACM, 2018. p. 290. ISBN 978-1-4503-5614-5.
Type
Proceedings paper
Departments
Annotation
This paper presents a performance comparison of various approaches of realization of status register suitable for maintaining (in)valid bits in mid-density memory structures implemented in Xilinx FPGAs. An example of a such structure with status register could be a dictionary for Lempel-Ziv based lossless compression algorithms where the dictionary has to be initialized before each run of the algorithm with minimum time and logic resources consumption. The performance evaluation of designs has been made in Xilinx ISE and Vivado toolkits for the Virtex-7 FPGA. This research has been partially supported by the CTU project SGS17/017/OHK3/1T/18 "Dependable and attack-resistant architectures for programmable devices" and by the project "E-infrastructure CESNET "modernization" no. CZ.02.1.01/0.0/0.0/16 013/0001797.
A Novel and Efficient Method to Maintain FPGA Embedded Memory Content with an Asymptotically Constant Time (Re)Initialization Designed for an IP Packet Lossless Compression
Authors
Bartík, M.; Ubik, S.; Kubalík, P.
Year
2016
Published
Počítačové Architektury & Diagnostika PAD 2016 - Sborník příspěvků. Brno: Vysoké učení technické v Brně, 2016. p. 89-92. ISBN 978-80-214-5376-0.
Type
Proceedings paper
Departments
Annotation
This paper describes analysis and implementation of a new method for maintaining valid content of FPGA memory blocks with an asymptotically constant time synchronous clear abilities, that can be used with advantage for (re)initialization to the one default value. This particular method is designed for the high-speed/high-throughput systems like LZ77 lossless algorithm based compression of IP (Internet Protocol) packets in 10 Gbps Ethernet networks, where a dictionary has to be(re)initialized before each run of the implemented algorithm.
Fast lossless compression algorithms
Authors
Bartík, M.; Ubik, S.; Kubalík, P.
Year
2015
Published
Sborník příspěvků PAD 2015. Zlín: Universita Tomáše Bati ve Zlíně, 2015, pp. 31-36. ISBN 978-80-7454-522-1.
Type
Proceedings paper
Departments
Annotation
This paper deal with the lossless compression algorithm LZ4 (based on the LZ77) and its suitability for multimedia data and universal packet compression in realtime for applications, that are sensitive on network latency.
LZ4 Compression Algorithm on FPGA
Authors
Bartík, M.; Ubik, S.; Kubalík, P.
Year
2015
Published
21st IEEE International Conference on Electronics, Circuits, and Systems. New York: Institute of Electrical and Electronics Engineers, 2015. p. 179-182. ISBN 978-1-4799-2451-6.
Type
Proceedings paper
Departments
Annotation
This paper describes analysis and implementation of
a LZ4 compression algorithm. LZ4 is derived from a standard
LZ77 compression algorithm and is focused on the compression
and decompression speed. The LZ4 lossless compression
algorithm was analyzed regarding its suitability for hardware
implementation. The first step of this research is based on
software implementation of LZ4 with regard to the future
hardware implementation. As a second step, a simple hardware
implementation of LZ4 is evaluated for bottlenecks in the original
LZ4 code. Xilinx Virtex–6 and 7–Series FPGAs are used to obtain
experimental results. These results are compared to the industry
competitor.