Ing. Jaroslav Borecký, Ph.D.

Proceedings paper

10.1109/DSD51259.2020.00111

Department of Digital Design

Testing of FPGA-based designs persists to be a challenging task because of the complex FPGA architecture with heterogeneous components, and therefore a complicated fault model. The standard stuck-at fault model has been found insufficient. On the other hand, very precise FPGA fault models have been recently devised. However, these models are often excessively complex and require a lot of resources (run-time, memory) to manipulate with. In this paper, we propose a simple yet efficient combined fault model comprising bit-flips in look-up tables and stuck-at faults in the rest of logic. On~top of this model, a dedicated SAT-based application-oriented ATPG has been designed. The main contribution of this paper is the evaluation of efficiency of the fault model with the respective ATPG by exhaustive hardware emulation of all possible SEUs in the configuration memory that may influence the functionality of the circuit implemented in the FPGA. We show that the obtained fault coverage reaches up to more than 99%, which makes the method applicable in practice. Even though combinational circuits are assumed only, the method can be used to quickly test safety-critical combinational cores.

Article

10.1002/navi.390

Department of Digital Design

This paper presents a new modified Single Block Zero-Padding (mSBZP) Partial Correlation Method (PCM) Parallel Code Search (PCS) algorithm for effective acquisition of weak GNSS tiered signal using coherent processing of its secondary code (SC) component. Two problems are discussed: acquisition of primary codes with longer period using FFT blocks of limited length, and the utilization of PCS in the presence of SC bit transition. The PCM and SC bit transition forms parasitic fragments in the Cross-Ambiguity-Function (CAF) to devaluate signal detection performance. A novel analysis of this mechanism and its impact is presented. A novel mSBZP-PCM-PCS algorithm is proposed, which does not degrade the CAF. Then, the algorithm is combined with SC bit transition removal schema and sequential search to construct an estimator for weak tiered signal acquisition. The performance of the method is demonstrated by analysis and computer simulation using Galileo E1C and GPS L1C-P signals.

Article

10.1016/j.micpro.2017.06.015

Department of Digital Design

This paper proposes a method improving the fault-coverage capabilities of Field Programmable Gate Array (FPGA) designs. Faults are mostly Single Event Upsets (SEUs) in the configuration memory of SRAM-based FPGAs and they can change the functionality of an implemented design. These changes may lead to crucial mistakes and cause damage to people and environment. The proposed method utilizes Concurrent Error Detection techniques and the basic architectures of actual modern FPGAs - the Look-Up Table (LUT) with two outputs. The main part of the paper is the description of the proposed method (Parity Waterfall) based on a cascade - waterfall - of several waves of inner parity generating the final parity of outputs of the whole circuit. The proposed Parity Waterfall (PWtf) method utilizes the (mostly) unused output of a two-output LUT to cover any single possible routing or LUT fault with a small area overhead. The encapsulation of the proposed PWtf method into a Duplication with Comparison scheme is presented in the second part of the paper. This encapsulation allows us to create a system containing two independent copies of all parts able to detect and localize any single fault (like common Triple Modular Redundancy method). Experiments are performed on the standard set of IWLS2005 benchmarks in our simulator. The results demonstrate differences between our proposed method and a similar existing technique - Duplication with Comparison (DwC), and between the encapsulated PWtf method and TMR. The proposed method has a lower relative overhead and requires a lower number of inputs and outputs.

Proceedings paper

10.1109/DSD.2016.91

Department of Digital Design

This paper proposes a method improving the faultcoverage capabilities of Field Programmable Gate Array (FPGA) designs. Faults are mostly single event upsets (SEUs) in the configuration memory of SRAM-based FPGAs and they can change the functionality of an implemented design. These changes may lead to crucial mistakes and cause damage to people and environment. The proposed method utilizes Concurrent Error Detection (CED) techniques and the basic architectures of actual modern FPGAs – the Look-Up Table (LUT) with two outputs. The Parity Waterfall method (based on a cascade – waterfall – of several waves of inner parity generating the final parity of outputs of the whole circuit) presented in our previous paper has been encapsulated into a Duplication scheme in this paper. This encapsulation allows us to create a system containing two independent copies of all parts able to detect and localize any single fault (like common Triple Modular Redundancy (TMR) method). Experiments are performed on the standard set of IWLS2005 benchmarks in our simulator. The results demonstrate differences between our proposed method in comparison with TMR – the proposed method has a lower relative overhead and requires a lower number of inputs and outputs.

Proceedings paper

10.1109/DDECS.2016.7482441

Department of Digital Design

This paper proposes a method for improvement of the fault-coverage capabilities of Field Programmable Gate Array (FPGA) designs. It utilizes Concurrent Error Detection (CED) techniques and the basic architectures of actual modern FPGAs the Look-Up Table (LUT) with two outputs. Proposed Parity Waterfall method is based on a cascade (waterfall) of several waves of inner parity generating the final parity of outputs of the whole circuit. The utilization of the (mostly) unused output of a two-output LUT allows the proposed method to cover any single possible routing or LUT fault with a small area overhead. The method is experimentally evaluated using the standard set of IWLS2005 benchmarks and using our simulator/emulator. The experimental results of the proposed parity waterfall method are compared with a similar existing technique (duplication with comparison). These results show that the area overhead is smaller than the overhead of the duplication with comparison method for all of the tested circuits and 100% fault coverage is achieved.

Proceedings paper

10.1109/BEC.2016.7743734

Department of Digital Design

In this paper we propose a SAT-based ATPG algorithm for application-oriented FPGA testing. For this purpose, a novel fault model is introduced which combines the stuck-at fault model for interconnects testing with the bit-flip model for LUT testing. The concept of SAT-based ATPG enables integrating these two models easily. Fault coverage and fault dominance of the two models is discussed in this paper, yielding suggestions for using the proposed combined model.

Proceedings paper

Department of Digital Design

This paper presents the method of dependability parameters improvement for systems based on unreliable components such as Field Programmable Gate Arrays (FPGAs). It combines concurrent Error Detection (CED) techniques, FPGA dynamic reconfigurations and our previously designed Modified Duplex System (MDS) architecture. The methodology is developed with respect to the minimal area overhead. It is aimed for practical applications of modular systems. Therefore it is applied and tested on the safety railway station system. This Fault-Tolerant (FT) design is tested to fulfill strict Czech standards [8]. The proposed method is based on static and partial dynamic reconfiguration of totally self-checking blocks which allows a full recovery from a Single Even Upset (SEU).

Proceedings paper

Department of Digital Design

Our research is focused on mission critical applications using SRAM based Field Programmable Gate Arrays (FPGAs).The main goal is to reach higher availability and dependability and low power using unreliable components (FPGAs) with respect to highest safety according to strict Czech standards. Our methodology is designed for fast applicatons and rapid prorotyping of modular systems, which are useful for fast development thanks to its regulars structure. The methodology combines Concurrent Error Detection (CED) techniques, FPGA dynamic recondfigurations and our previously designed Modified Duplex Systems (MDS) architecture. The methodology tries minimizes area overhead. It is aimed for practical applications of modular systems, which are composed from blocks. We applied and tested it on the safety railway station system. The proposed method is based on static and partial dynamic reconfiguration of totally self-checking blocks which allows a full recovery from a Single Even Upset (SEU).

Proceedings paper

10.1109/DSD.2014.54

Department of Digital Design

This paper presents the method of dependability parameters improvement for systems based on unreliable components such as Field Programmable Gate Arrays (FPGAs). It combines Concurrent Error Detection (CED) techniques [4], FPGA dynamic reconfigurations and our previously designed Modified Duplex System (MDS) architecture. The methodology is developed with respect to the minimal area overhead and high availability. It is aimed for mission critical practical applications of modular systems. Therefore it is applied and tested on the safety railway station system, where all these parameters are required. This Fault-Tolerant (FT) design is modeled and tested to fulfill strict Czech standards [7]. The proposed method is based on static and partial dynamic reconfiguration [5] of totally self-checking blocks which allows a full recovery from a Single Even Upset (SEU). This method is compared with triple module redundancy technique.

Proceedings paper

10.1109/DSD.2012.86

Department of Digital Design

This paper compares four different redundancy methods, which includes parity code, partial duplication and their combinations, with two standard methods (Duplex and Triple Module Redundancy). Two main attributes are observed: the Total size of system including overhead caused by redundancy addition and steady-state availability - dependability parameter defining the readiness for correct service of a system.

Proceedings paper

10.1109/DSD.2011.42

Department of Digital Design

FPGAs are susceptible to many environment effects that can cause soft errors (errors which can be corrected by the reconfiguration ability of the FPGA). Two different fault models are discussed and compared in this paper. The first one - Stuck-at model - is widely used in many applications and it is not limited to the FPGAs. The second one - Bit-flip model - can affect SRAM cells that are used to configure the internal routing of the FPGA and to set up the behavior of the Look-Up Tables (LUTs). The change of the LUT behavior is the only Bit-flip effect considered in this paper. A fault model analysis has been performed on small example designs in order to find the differences between the fault models. This paper discusses the relevance of using two types of models Stuck-at and Bit-flip with respect to the dependability characteristics Fault Security (FS) and Self-Testing (ST). The fault simulation using both fault models has been performed to verify the analysis

Proceedings paper

Department of Digital Design

This paper deals with a description of the method, how to increase dependability parameters (safety and reliability) of a system based on programmable hardware (FPGAs). This paper combines Concurrent Error Detection (CED) techniques, FPGA dynamic reconfigurations and our Modified Duplex System (MDS) architecture. The methodology is developed with respect to minimal area overhead and possible future low-power SoC (System on a chip) design. Our proposed methodology is great intended for practical applications, therefore our methodology is evaluated by safety railway station system. It is aimed especially for modular systems. The method is based on static and partial dynamic reconfiguration of totally self-checking blocks. The type and size of blocks to reconfigure depends on the used architecture and on the particular construction of a safety device for the particular railway station.

Proceedings paper

Department of Digital Design

This paper presents future work, which the main goal is to find a solution for interconection between reconfigurable blocks and keep fault secure parameters. Described method will use a partial reconfiguration to obtain self-repair ability. Our concept will be proved on a practical problem, which is implementing the railway station system in the FPGA.

Proceedings paper

Department of Digital Design

This paper summarizes previous work, which observed design finite state machines of MOORE type with self-checking architecture. My concept is proved on a practical problem, which is implementing the railway station system in the FPGA. The safety device for any configuration of railway station can be built from five basic blocks. Each block is based on a finite state machine of MOORE type. My methodology is intended for final implementation in FPGA and hence SEU faults occurring in the system is assumed.

Proceedings paper

10.1109/DSD.2010.112

Department of Digital Design

A method how to improve the coverage of single faults in combinational circuits is proposed. The method is based on Concurrent Error Detection, but uses a fault simulation to find Critical points - the places, where faults are difficult to detect. The partial duplication of the design with regard to these critical points is able to increase the faults coverage with a low area overhead cost. Due to higher fault coverage we can increase the dependability parameters. The proposed modification is tested on the railway station safety devices designs implemented in the FPGA.

Proceedings paper

Department of Digital Design

Our aim is to create a methodology for FPGA industrial applications with respect to area, speed, power consumption and reliability optimizations (both fail safe and fault-tolerant). We take into account different types of faults, the way they affect the circuit (Single Event Upset, Single Event Latchup, Delay faults etc.) and their injection into design (insertion into bitstream, edif, behavioral description or saboteur method). We need to create formal dependability models that are able to model mentioned faults and reconfifiguration ability of FPGAs. We use well-known Markov Chains and Stochastic Petri nets. The usage of both types of models is similar and they are mutually convertible. This paper describes the main problems how to obtain relevant and comparable results.

Proceedings paper

10.1109/DSD.2009.210

Department of Digital Design

The method how to design a safety device of railway station efficiently and scalable is proposed. The safety device for any configuration of railway station can be built from five basic blocks. These basic blocks are connected together with universal interface. Each block is based on a finite state machine. The finite state machines are "Moore" type. Each state machine is divided into three basic parts, where each part is designed as a self-checking circuit ensuring fault detection. Our methodology is intended for final implementation in FPGA and hence SEU faults occurring in the system is assumed.