prof. Ing. Hana Kubátová, CSc.

Specialist supervisor: Ing. Tomáš Čejka, Ph.D.

The aim of this work will be research and development of algorithms for detection, identification, and mitigation of security threats and anomalies in computer networks, especially Internet of Things (IoT). From the perspective of network security, it is necessary to consider the IoT area as a threat not only for IoT devices but also for other devices and services in the Internet, since the IoT network can easily become a source of trouble (as it was observed in recent history). It is necessary to monitor IoT network traffic, derive meta information about the traffic based on events and device behavior, and use such meta information for identification and mitigation of threats, choosing a suitable mitigation strategy.

The goal of the dissertation thesis will be to find suitable ways to create long-term models of communication, which represent negative and positive events, and to use such models for anomaly detection, identification and mitigation of sources of troubles with low latency. Dissertability of this topic is based on non-trivial challenges such as processing and filtering huge volume of network traffic and creation of models of network traffic, discovering anomalies, identification of sources of trouble and choosing correct strategy of mitigation of malicious traffic. Contrary to classic IP networks, the IoT communication lays mainly in specific physical layers. This brings new potential attack vectors that are not detectable using ordinary IP traffic analysis. Therefore, it is needed to find new approaches to IoT traffic monitoring. The base of the work will be a research in the area of statistical methods, probabilistic models, and usage of algorithms of artificial intelligence.

Due to the modern networks bandwidth and on-line monitoring requirements, it is necessary to design and develop algorithms using a decomposition among hardware and software components and to use suitable technologies for hardware acceleration (e.g., FPGA).

Specialist supervisor: Ing. Martin Kohlík, Ph.D.

Currently used dependability models are often based on simplified processes leading to unrealistic estimations of dependability and reliability parameters of the modeled systems [1] or rough pessimistic estimations [2]. The aim of the research should be a methodology of the dependability model design allowing fast and accurate calculations of the dependability parameters of the system. The methodology should take over-time changes (e.g. aging, maintenance, repairs) of the system, the structure (blocks and their fail-safes) of the system, and the ways of acquiring dependability parameter data from real applications into account [3].

• [1] Electronic Reliability Design Handbook - MIL-HDBK-338B. US Department of Defense, 1998.
• [2] M. Kohlík, "Hierarchical Dependability Models Based on Markov Chains", Dissertation thesis, Czech Technical University in Prague, 2015.
• [3] Daňhel, M.: "Prediction and Analysis of Mission Critical Systems Dependability", Dissertation thesis, Czech Technical University in Prague, 2018.

The research of methods and processes in the design of systems with pre-defined reliability parameters using programmable hardware sources (FPGA, processors). The reaserch of the impact of a redundancy at different levels (space, time, software, hardware) to the attack resistance of the whole system. The research of automatization methods of the design processes including the dependability models construction and dependability parameters computations. Partial results and proposed methods will be evaluated by real-life application and benchmarks.

The research area will be based on formal methods and models (Petri Nets, Markov chains, UML diagrams) to use them for simplificationa and automatization of digital design process. The connection of verification methods and dependability modeling at all design periods to obtain an optimized structure according different parameters is assumed. The aim should be the combination of different models and detailed study of their relations and possible automatic conversions. Partial results and proposed methods will be evaluated by real-life applications and benchmarks. An integral part of the topic is the study of possible new models used in industry and / or research.

Specialist supervisor: Ing. Pavel Kubalík, Ph.D.

Main aims of this research are:

- Design of new architectures based on on-line error control codes available for implementation in reconfigurable hardware (FPGAs). The fulfillment of required reliable parameters is essential, together with a low area overhead, appropriate operational frequency, and low power consumption for mission-critical systems (intelligent cars, robots, etc.) where FPGA are more and more used due to their properties (and price).

- Proposal of appropriate methods to automatically select the best type of fault-tolerance and safety with respect to a particular application, its requirements and the necessary constrains, including design speed.

- Utilization of existing models and modifying them to solve this problem at the system level, and linking them to the hierarchical dependability models, created at the department.

The target platform will be FPGA circuits allowing fault recovery of a part design or completely change of an implemented function. The research will be mainly focused on the utilization of new error control codes for an optimized architecture enabled error detection and correction suitable for FPGA. The standard known fault-tolerant structures such as TMR or a duplex will be taken into account, too.

All proposed architectures and the partial results will be tested on standard known benchmarks and on dedicated sets of own circuits. The evaluation criterion will be mainly focused on realistic calculations of dependable parameters, together with low area occupation requirements.

The proposed research has to verify possibilities, how to achieve (and guarantee) predefined system design constraints (size, power-consumption, dependability characteristics, fault-tolerance and attack-resistance levels via trade-off between hardware and software parts and types.

It is supposed to use Codasip system and RISC-V processor (open-source hardware instruction set architecture (ISA) based on established reduced instruction set computer (RISC) principles, designed (not only) for embedded applications, where low-power and performance are emphasized. Codasip can provide their processors with high-level tools that enable to configure the RISC-V cores, to automatically generate toolchains and synthesizable, human-readable Verilog RTL. Codasip system (https://codasip.com/) offers a verification environment, too.

The research will contain proper evaluation of obtained architecture by improved dependability models. The possible methods will be ISA improvement (e.g. adding the cryptographic instructions, specialized block, using of more application-specific processors). Final experiments will be performed by simulations and FPGA implementations.

prof. Ing. Hana Kubátová, CSc.

Ing. Jaroslav Borecký, Ph.D.

Department of Digital Design

This work deals with scheduling algorithms for real-time systems, examines and modifies the real-time operating system FreeRTOS. FreeRTOS is specially developed for small embedded systems to meet both user and memory requirements. After a~detailed description of the priority scheduler adopted by FreeRTOS, two learning schedulers are proposed: the first is based on the known Earliest Deadline First Algorithm (EDF), the second is based on the Least Laxity First Algorithm (LLF), originally developed for multiprocessor systems. For each proposed scheduler, a description of the scheduler's functionality, a demonstration of the work of the scheduling algorithm and subsequent implementation in FreeRTOS is given. Then the correctness of the planning algorithms implemented in FreeRTOS is verified by a test. Planning algorithms were selected on the basis of usefulness in the bachelor's course BI-SRC at FIT CTU in Prague.

Thesis on DSpace

prof. Ing. Hana Kubátová, CSc.

Ing. Jaroslav Borecký, Ph.D.

Department of Digital Design

prof. Ing. Hana Kubátová, CSc.

Department of Software Engineering

This thesis work is deeply about the scheduling algorithms in operating system schedulers. The algorithms that are used for implementing a scheduler for a real time operating system is vital to the lifecycle and outcome of any set of real time applications that get executed. When it comes to real time applications, especially with the hard real time applications, the deadlines and response times required by the applications have to be followed as strictly as possible. There are various scheduling algorithms that are used in many different scheduler designs. However, not all of them pursue the above objective for real time applications. Therefore, we discuss and study various scheduling algorithms in a technically detailed manner in order to determine the ones that would be applicable for real time operating systems that would run real time embedded applications. Later, we implement and integrate the scheduling algorithms that are chosen for real time applications based on our study, to an open source real time operating system FreeRTOS in C programming language, of course. Then as a final step to this study, we run a real time embedded application together with our modified FreeRTOS with our custom implementations for the scheduler algorithms are included, on ARM Cortex-M3 microcontroller architecture by using QEMU with respect to predetermined design constraints such as processing speed, determinism, size, maximum operating frequency, deadline fulfillment, etc.. We demonstrate functioning scheduling algorithms running in a real time operating system executing a real time application without having to own a hardware by QEMU, which makes testing and scheduling analysis of real time applications and scheduling algorithms on all software. We also compare and evaluate the performance of the implemented algorithms in order to better understand how each of the algorithms behave under certain circumstances which will help us choose better suitable algorithms for our real time applications.

Thesis on DSpace

doc. Ing. Hana Kubátová, CSc.

Ing. Martin Kohlík, Ph.D.

Department of Digital Design

Primary focus of this thesis is to find a solution for converting a Petri net description in PNML language into synthesizable code for FPGA devices in VHDL language. The first part introduces a concept of Petri nets themselves, their variations and practical examples. Next part deals with available tools for modeling Petri nets and explains their positives and negatives. Third part presents the PNML standard and shows a possible method of implementing a Petri net in FPGA platform. The conversion itself will be carried out by created application and demostrated on a Petri net model example. At the end the thesis comes with a conclusion of functionality and utilization of this solution.

Thesis on DSpace

doc. Ing. Hana Kubátová, CSc.

Department of Digital Design

This master thesis contains theoretical basics of processor typology with aim on processor VLIW family. The reader will get familiar with Codasip IDE, in which a design of Codix VLIW processor is implemented. The correct implementation of processor core is validated using functional verification. The result of this master thesis is processor Codix VLIW on Xilinx Zynq platform.

Thesis on DSpace