Ing. Vojtěch Miškovský, Ph.D.

Theses

Master theses

Software toolkit for side-channel attacks

Author
Petr Socha
Year
2019
Type
Master thesis
Supervisor
Ing. Vojtěch Miškovský, Ph.D.
Reviewers
Dr.-Ing. Martin Novotný
Summary
Side-channel cryptanalysis pose a serious threat to many modern cryptographic systems. Typical side-channel attack consists of an active phase, where data are acquired, and an analytical phase, where the data get examined and evaluated. A software toolkit is presented in this thesis, which includes support for cryptographic device control, oscilloscope data acquisition, data preprocessing, statistical analysis and evaluation of the attack. The toolkit is composed of non-interactive text-based utilities with a modular plug-in architecture, and it is released under open-source licence.

Fast data-acquisition tools for side-channel analysis in FPGA

Author
Ondřej Semrád
Year
2020
Type
Master thesis
Supervisor
Ing. Vojtěch Miškovský, Ph.D.
Reviewers
Ing. Petr Socha
Summary
To mount a power analysis attack on a cryptographic device, one has to acquire up to millions of power traces of the attacked device. The goal of this thesis is to create a toolkit which will make the power traces acquisition faster whilst supporting as many different cryptographic schemes as possible. The toolkit will focus on hardware implentations of cryptographic schemes in FPGA.

Security analysis of electronic control units for automobiles

Author
Matúš Olekšák
Year
2022
Type
Master thesis
Supervisor
Ing. Vojtěch Miškovský, Ph.D.
Reviewers
Ing. Petr Socha, Ph.D.
Summary
This work deals with testing the security of control units for cars, more specifically, secure onboard communication via the CAN bus. Side-channel attack, flash of modified firmware, and extraction of bootloader over JTAG were attempted. The result is a successful attack with correlation power analysis of SipHash algorithm. However, I failed to use it for a real control unit, because of inability to find the computation in the measured data. The benefit of this work is the analysis of possible attacks on control units and successful side-channel attack on SipHash.

Implementation of side-channel analysis methods based on machine learning

Author
Zdeněk Muzika
Year
2025
Type
Master thesis
Supervisor
Ing. Vojtěch Miškovský, Ph.D.
Reviewers
Ing. Petr Socha, Ph.D.
Summary
This thesis focuses on the implementation of deep learning methods in side-channel analysis techniques. It explores both side-channel analysis and deep learning methodologies. The analyzed methods are implemented into a toolkit that enables their easy application. The developed tool is then used in a series of experiments to verify its functionality and evaluate the employed techniques.

Side-channel analysis of SipHash in FPGA

Author
Vít Mašek
Year
2025
Type
Master thesis
Supervisor
Ing. Vojtěch Miškovský, Ph.D.
Reviewers
Ing. Matúš Olekšák
Summary
Side-channel attacks represent a critical threat to the security of cryptographic devices, exploiting unintended physical leakages rather than mathematical vulnerabilities. This thesis focuses on evaluating the side-channel resistance of the SipHash algorithm, a lightweight ARX-based pseudorandom function, when implemented in FPGA. Although ARX ciphers are often considered resistant to such attacks, recent research suggests otherwise. A complete and configurable implementation of SipHash for the ChipWhisperer CW308 FPGA platform is presented, along with a measurement setup. Power consumption of the implementation is thoroughly evaluated using statistical leakage assessment methods. Detected vulnerabilities are then exploited in a practical side-channel attack. The results demonstrate that even ARX-based designs like SipHash require active consideration of side-channel countermeasures. This thesis provides valuable insights into the real-world security of the SipHash cipher and contributes to the broader understanding of side-channel threats in modern embedded systems.

Side-channel analysis of ChaCha20

Author
Lukáš Daněk
Year
2025
Type
Master thesis
Supervisor
Ing. Vojtěch Miškovský, Ph.D.
Reviewers
Ing. Matúš Olekšák
Summary
This thesis investigates the vulnerability of the ChaCha20 stream cipher to side-channel attacks, focusing on its software implementation in embedded systems. ChaCha20 is based on the ARX design principle, which relies exclusively on Addition, Rotation, and XOR operations, which are generally considered resistant to side-channel leakage. However, recent research demonstrates that even ARX constructions can be susceptible to leakage when implemented in practice. The main goal of this work is to evaluate the security of ChaCha20 against power analysis attacks. The cipher was evaluated on two widely used platforms, XMEGA and STM32F3, using the ChipWhisperer side-channel analysis framework. A thorough leakage assessment was conducted using specific and non-specific t-tests to identify exploitable leakage points. In the case of nonce misuse, full recovery of the keystream was demonstrated via a successful CPA attack. This scenario serves both as evidence of ChaCha20's vulnerability when used improperly and as validation of the attack setup and methodology. In scenarios with proper nonce usage, full key recovery was not achieved through CPA on either platform. A dedicated experiment on the feasibility of Differential Power Analysis (DPA) was also conducted, which did not yield any exploitable results. However, a novel CPA-based method for recovering key bytes stored in the first column of the ChaCha20 state was proposed and experimentally verified. This methodology leverages correlation in the second round of the cipher and applies inverse operations to reconstruct the original key bytes.

Power trace preprocessing for side-channel analysis of device with high clock jitter

Author
Tereza Horníčková
Year
2025
Type
Master thesis
Supervisor
Ing. Vojtěch Miškovský, Ph.D.
Reviewers
Ing. David Pokorný
Summary
Side-channel attacks and measures against them have been a hot topic for decades. Over the years, countless ways to prevent the attacker from gleaning sensitive information have emerged. Temporal misalignment of the trace either through random delay inserts or unstable clock is one such countermeasure. In response, numerous methods of realignment were proposed. This thesis researches these methods and uses one to help detect leakage from a chip with unstable clock.