Ing. Vojtěch Miškovský, Ph.D.

2025 - 2027

The ACDRC Embedded AI Processor for Automotive Applications project aims to intelligent driving technologies enhance driving safety through sensing, analysis, and decision-making. Central to these technologies is the ability to perceive the surrounding environment using sensors, which collect data and process it using embedded AI processors. These processors provide efficient AI computation, critical for intelligent driving systems machine learning (ML) and artificial intelligence (AI) techniques. Current embedded AI processors are often designed for general purposes, which may not meet the stringent requirements of automotive applications, such as low power consumption, high efficiency, and high performance. The specific needs of automotive intelligent driving applications demand optimized solutions. This project aims to develop an FPGA-based embedded AI processor optimized for specific automotive intelligent driving applications. The processor will handle 1Mp30 image signals, outputting detected object boundary coordinates and object categories.

2017 - 2019

This project proposal will study and design architectures which are able to tolerate faults, attacks, and unreliable sensory inputs especially in programmable devices (FPGAs), microcontroller systems and embedded systems with artificial intelligence integrated. This is typically achieved by introduction of redundancy by replicating critical circuits or by combining multiple sensory inputs. Security of devices, i.e., their resistance to malicious attacks, is the second extremely important aspect of today. Security is also often achieved by redundancy, aiming at obscuring data. The interaction between techniques for fault-tolerant, sensory robust and attack-resistant design will be studied. The intersection of all fields and the influence of controllability, observability, and redundancy will be studied.

2016

This project proposal will study and design architectures which is able to tolerate faults in programmable devices (FPGAs). This is typically achieved by introduction of redundancy. Security of devices, i.e., their resistance to malicious attacks, is the second extremely important aspect of today. The security is also often achieved by redundancy, aiming at obscuring data. The interaction between techniques for fault-tolerant and attack-resistant design will be studied. The crossing points of both fields, the influence of controllability, observability, and redundancy will be studied.

2017 - 2019

The Internet of Things (IoT) is increasingly becoming part of our everyday life. Therefore, electronic IoT devices need to be carefully designed, taking into account data security and privacy. Putting in place security and privacy measures should introduce a minimal overhead in the system's power/energy consumption, cost and operational delay. Additionally, since IoT devices are everywhere, attackers can be in the vicinity of the device, which stresses the need for protection against side-channel analysis (SCA) attacks. These attacks exploit the use of side-channels, which are information channels that are unintentionally present in electronic devices and which potentially leak secret information. Examples are the power consumption, the electromagnetic radiation and the timing behaviour of the electronic device. In both academia and industry, SCA countermeasures are being developed and deployed. However, as SCA attacks become more and more sophisticated, continuously evolving countermeasures are necessary to protect the electronic devices of the future. This project proposes the use of dynamic hardware reconfiguration as a countermeasure against one of the most exploited types of SCA attacks, namely power analysis attacks. The goal is to randomly change the hardware circuit without altering the input-output behaviour of the chip. Since power analysis attacks are strongly based on the knowledge of the circuit, this is a very promising countermeasure. Another advantage is that dynamic hardware reconfiguration can be used as an add-on to other countermeasures. The project focuses on dynamic hardware reconfiguration on FPGAs (field-programmable gate arrays). It will result in proof-of-concept implementations that will be evaluated for power analysis attack resistance. The experimental results are crucial for the definition of a European project proposal that develops an automated tool flow and industry-driven use cases to show the effectiveness of the approach.

2016

Prague Embedded Systems Workshop (PESW 2016, http://pesw.fit.cvut.cz/2016/) je již čtvrtým ročníkem akce přednostně určené pro studenty (doktorandy i magisterské studenty) nejen z České republiky. Hlavní náplní a cílem jsou ústní prezentace a poskytnutí velkého prostoru pro diskuse o zajímavých výzkumných výsledcích i realizačních výstupech v oblasti, která má vztah k návrhu vestavných systémů, a to k jejich realizaci, verifikaci, syntéze, testovatelnosti i zajímavým aplikacím. Ohlasy minulých třech ročníků byly jednoznačně kladné, proto připravujeme již čtvrtý ročník PESW 2016 opět v hotelu Academic v Roztokách u Prahy, který nás zcela uspokojil jednak svou polohou a jednak službami. Hlavním organizátorem je katedra číslicového návrhu FITu, zejména členové výzkumné skupiny "Digital Design & Dependability Research Group" (http://ddd.fit.cvut.cz/). Od minulého ročníku se opět podařilo rozšířit mezinárodní programový výbor, máme přislíbenou účast doktorandů, jejich školitelů a dalších aktivních účastníků z universit z Tel Avivu (Izrael), University of Leicester (UK), University di Pavia (Itálie), Zelené Gory a Varšavy (Polsko), FIIT z Bratislavy, Západočeské university, firmy EaToN, FELu a FITu i z Brněnského VUT. CfP rozesíláme i na další pracoviště. Vzhledem k mezinárodní účasti probíhá workshop celý v angličtině. SCOPE: The workshop PESW 2015 addresses emerging issues, hot problems, new solution methods, and their hardware and software implementations in the fields of digital and mixed-signal system design. It is especially focused on dependable and low power design, and testing methods related to the SoC technology and modern embedded applications. The workshop topics include (but are not limited to): Programmable/re-configurable/adaptable architectures SoC and NoC design and testing Digital design optimization methods Architectures and hardware for security applications On-line and off-line error detection and correction Fault-tolerant control systems design me