Ing. Stanislav Jeřábek

2015

The internal structure of programmable devices is complex and unrevealed, which makes the design of applications with provable dependability and security difficult. At the theoretical level, the interaction between techniques for fault-tolerant and security attack-resistant design is not well understood. The crossing point of both fields, the notions of controllability, observability, and redundancy will be studied. Application architectures, where dependability and security support each other will be designed. Moreover, absorbing their features into the structure of a programmable device will be demonstrated. To prove and evaluate these achievements, methods to construct realistic models of applications will be developed. The gap caused by the complex and obscure structure of the devices will be overcome by model calibrations, that is, by aligning its predictions with the results of real device tests. Currently, the structural complexity of the device prevents design evaluation using detailed models, requiring to simplify and hierarchize the model while maintaining its relevance.

2017 - 2019

This project proposal will study and design architectures which are able to tolerate faults, attacks, and unreliable sensory inputs especially in programmable devices (FPGAs), microcontroller systems and embedded systems with artificial intelligence integrated. This is typically achieved by introduction of redundancy by replicating critical circuits or by combining multiple sensory inputs. Security of devices, i.e., their resistance to malicious attacks, is the second extremely important aspect of today. Security is also often achieved by redundancy, aiming at obscuring data. The interaction between techniques for fault-tolerant, sensory robust and attack-resistant design will be studied. The intersection of all fields and the influence of controllability, observability, and redundancy will be studied.

2016

This project proposal will study and design architectures which is able to tolerate faults in programmable devices (FPGAs). This is typically achieved by introduction of redundancy. Security of devices, i.e., their resistance to malicious attacks, is the second extremely important aspect of today. The security is also often achieved by redundancy, aiming at obscuring data. The interaction between techniques for fault-tolerant and attack-resistant design will be studied. The crossing points of both fields, the influence of controllability, observability, and redundancy will be studied.

2020 - 2022

The project deals with the digital design focused on embedded systems. It will cover the study of the latest trends in technologies and their use in mission-critical applications. The design of such systems must take into account not only functionality but also other constraints; they must meet the required levels of reliability, security, attack resistance, size, power consumption, and real-time guarantees. Therefore, we will use new methods, algorithms and design tools (EDA tools) to find, design and modify suitable models that will allow to test, predict and formally verify the required functions and behavior of the system.

2017 - 2019

The Internet of Things (IoT) is increasingly becoming part of our everyday life. Therefore, electronic IoT devices need to be carefully designed, taking into account data security and privacy. Putting in place security and privacy measures should introduce a minimal overhead in the system's power/energy consumption, cost and operational delay. Additionally, since IoT devices are everywhere, attackers can be in the vicinity of the device, which stresses the need for protection against side-channel analysis (SCA) attacks. These attacks exploit the use of side-channels, which are information channels that are unintentionally present in electronic devices and which potentially leak secret information. Examples are the power consumption, the electromagnetic radiation and the timing behaviour of the electronic device. In both academia and industry, SCA countermeasures are being developed and deployed. However, as SCA attacks become more and more sophisticated, continuously evolving countermeasures are necessary to protect the electronic devices of the future. This project proposes the use of dynamic hardware reconfiguration as a countermeasure against one of the most exploited types of SCA attacks, namely power analysis attacks. The goal is to randomly change the hardware circuit without altering the input-output behaviour of the chip. Since power analysis attacks are strongly based on the knowledge of the circuit, this is a very promising countermeasure. Another advantage is that dynamic hardware reconfiguration can be used as an add-on to other countermeasures. The project focuses on dynamic hardware reconfiguration on FPGAs (field-programmable gate arrays). It will result in proof-of-concept implementations that will be evaluated for power analysis attack resistance. The experimental results are crucial for the definition of a European project proposal that develops an automated tool flow and industry-driven use cases to show the effectiveness of the approach.

2014

The goal of the project is the research and development of security features of current information systems. The emphasis is placed on data and communicaton security at both hardware and software levels. The Network Security Research Group and the Applied Numerics and Cryptography Research Group have been involved in research of various security elements and aspects of information systems. It is especially development in the area of cryptanalysis of block and stream ciphers, in network security, in smart-card security, and in reverse engineering. The proposed project also addresses these thematic research areas.

2023

PhD studenti katedry číslicového návrhu FITu za podpory svých školitelů se rozhodli uspořádat pracovní setkání - workshop s tématikou vztahující se k současným výzkumným i aplikačním výzvám, které podporují masivní rozvoj nových technologií a spolu s tím i možnost využití čím dál složitějších a chytřejších algoritmů. Tématika vestavných systémů v sobě zahrnuje mnoho výzkumných výzev v oblasti computer science: kritické aplikace (v dopravě i ve vesmíru), umělou inteligenci např. pro ovládání robotů, návrhy nových architektur odolných proti útokům a/i poruchám, real-time komunikaci na velké vzdálenosti, sběr dat z chytrých nízkopříkonových senzorových systémů, aj. Jinými slovy současný svět informatiky je propojený a cílem naší nové akce je propojit i studenty a jejich aktivity tak, aby jejich prezentace dílčích výsledků nebo zdánlivě slepých cest cílila ke vzájemné spolupráci a lepším týmovým a hlavně disertabilním výstupům. Chceme navázat na dříve pořádanou doktorskou konferenci na FITu, která ovšem byla povinná a nebyla výjezdní (a byla také podporovaná interním grantem SVK). Chceme podpořit nejen spolupráci na bázi poslechu přednášek, ale hlavně podpořit kuloární diskuse a hledání společných a vzájemně využitelných výzkumných témat. Organizátoři jsou zejména členové výzkumné skupiny "Digital Design & Dependability Research Group" (http://ddd.fit.cvut.cz/), a to hlavně PhD studenti, kteří budou předsedat jednotlivým sekcím a vyzkouší si tak prakticky roli "session chairs" na klasických konferencích. Bude připraven elektronický sborník abstraktů a soubor podkladů pro prezentace. Účast studentů magisterského, případně bakalářského studia, kteří uvažují o doktorském studiu je vítána. Hlavní náplní workshopu budou ústní prezentace a zároveň poskytnutí velkého prostoru pro diskuse o nejnovějších (třeba i rozpracovaných) výzkumných výsledcích i realizačních výstupech v oblasti, která má vztah k návrhu a aplikaci vestavných systémů, a to k jejich realizaci, verifi