Ing. Jiří Kašpar

Theses

Bachelor theses

Conversion of Graphs in Microsoft Excel Documents to the LaTeX

Author
Milan Klouček
Year
2015
Type
Bachelor thesis
Supervisor
Ing. Jiří Kašpar
Reviewers
doc. Ing. Ivan Šimeček, Ph.D.
Summary
This work implements converter from Microsoft Office Excel charts into the \LaTeX. It analyses used data patterns, suggests principles of conversion between them and verifies reliability of the conversion. Suggested principles of conversion are then being implemented in Visual Basic for Application.

Ballroom dance simulation

Author
Jan Karafiát
Year
2014
Type
Bachelor thesis
Supervisor
Ing. Jiří Kašpar
Reviewers
Ing. Jan Trávníček, Ph.D.

Conversion of tables in Microsoft Excel documents to the LaTeX and to the DokuWiki.

Author
Viktória Hroncová
Year
2014
Type
Bachelor thesis
Supervisor
Ing. Jiří Kašpar
Reviewers
doc. Ing. Ivan Šimeček, Ph.D.

Command Line Description Generator

Author
Nikita Evstigneev
Year
2021
Type
Bachelor thesis
Supervisor
Ing. Jiří Kašpar
Reviewers
Ing. Jan Trdlička, Ph.D.
Summary
This bachelor thesis analyzes the problem of generating command description in CLD language from its manual page, which then can be used in dclsh shell. The goal of this work is to automate the process of writing command descriptions in order for dclsh shell to achieve more convenient communication between user and shell.

Axigen Mail Server Scalability on Various Hypervisors

Author
Petr Fortin
Year
2015
Type
Bachelor thesis
Supervisor
Ing. Jiří Kašpar
Reviewers
Ing. Jiří Smítka
Summary
The work is focused on comparing the performance of hypervisors with mail server application Axigen . The text includes an overview of approaches to virtualization, overview of used hypervisors and their properties, research of tools to generate load of mail server and tools for measuring server performance. The aim of this study was to compare the performance of Axigen mail server on physical and virtual machines, and to see where this application can achieve the best possible performance.

Conversion of Microsoft Powerpoint slides to DokuWiki (edux) format

Author
Michal Daňhelka
Year
2012
Type
Bachelor thesis
Supervisor
Ing. Jiří Kašpar
Reviewers
Ing. Tomáš Zahradnický, Ph.D.

DiskSim Simulator Enhancements

Author
Jana Berušková
Year
2019
Type
Bachelor thesis
Supervisor
Ing. Jiří Kašpar
Reviewers
doc. Ing. Ivan Šimeček, Ph.D.
Summary
This bachelor thesis analyzes how disk simulator DiskSim simulates RAID arrays and extends it with functions that allow it to simulate the work with the data even when one or more disks are broken. The data security issue is resolved in RAID5, and RAID6 by using the Reed-Solomon scheme that allows the data to be reconstructed on multiple disks. The completed simulator can then be used in the education about data storage and in practice to compare different configurations.

Storage Network Command Simulator - server and storage part

Author
Dmitrii Vekshin
Year
2019
Type
Bachelor thesis
Supervisor
Ing. Jiří Kašpar
Reviewers
Ing. Jan Trdlička, Ph.D.
Summary
The primary goal of this bachelor thesis is to create storage and server parts within the project Storage Network Command Simulator. The first part of the thesis presents an analysis of existing storage networks, data storages, their command interfaces and data storages simulators. The next part is the development, implementation and testing simulators of storage and server components, with supporting data operations modeling.

MySQL Scalability on Various Hypervisors

Author
Pavel Beneš
Year
2015
Type
Bachelor thesis
Supervisor
Ing. Jiří Kašpar
Reviewers
Ing. Josef Hlaváč, Ph.D.

Conversion of Microsoft Word documents to DokuWiki (edux) format

Author
Pavel Kult
Year
2012
Type
Bachelor thesis
Supervisor
Ing. Jiří Kašpar
Reviewers
Ing. Michal Šoch, Ph.D.

DiskSim Simulator GUI

Author
Kamil Jakubovič
Year
2017
Type
Bachelor thesis
Supervisor
Ing. Jiří Kašpar
Reviewers
doc. Ing. Ivan Šimeček, Ph.D.
Summary
This bachelor thesis deals with a design and implementation of a graphic user interface to the disk simulator DiskSim. The main target of the thesis is an easy and clear work with the simulator with an emphasis on a graphic representation of its results. Easy installation, platform independence, and future extensibility are the key features of the interface. These keys together with a result of already existing solutions lead in a network architecture client-server. The outcome of the practical part is a standalone web server run under a minimalist framework Bottle joining a user web browser and the simulator. The simulator can also be controlled remotely and noninteractively thanks to the used REST API. The web browser screenshots listed in the implementation chapter shows the easiness of the interface and the illustrative representation of simulator results.

Master theses

Multiprocessor/Multicore System Simulation with the GEM5 Simulator

Author
Robert David
Year
2014
Type
Master thesis
Supervisor
Ing. Jiří Kašpar
Reviewers
doc. Ing. Ivan Šimeček, Ph.D.

Simulation of Shared Cache Hierarchy

Author
Jindřich Čapek
Year
2015
Type
Master thesis
Supervisor
Ing. Jiří Kašpar
Reviewers
doc. Ing. Ivan Šimeček, Ph.D.
Summary
This thesis contains implementation of Shared Cache Hierarchy with cache coherency protocol MOESI in GEM5 simulator. This thesis contains short description of GEM5 simulator and its memory system, description of MOESI coherency protocol, description of implementation and connection between cache controllers. We simulated a system with two eight-core processors with three-level cache hierarchy. Implementation was tested with test embedded in GEM5 simulator. We ran selected benchmarks from PARSEC and SPLASH-2 suits and compared results with real system.

Cache operation analyser for the GEM5 simulator

Author
Jakub Pavčo
Year
2017
Type
Master thesis
Supervisor
Ing. Jiří Kašpar
Reviewers
doc. Ing. Ivan Šimeček, Ph.D.
Summary
The thesis concernes simulation of operations cache memory. Goal of the thesis is development cache memory analyzer and verify it at bechmarks PARSEC and SPLASH programs. The thesis contains four chapter. First chapter analyses simulator gem5 and its tracing possibilities. Second chaper analyses using of address space and analyses functions thats modify address space. Third chapter describes design of development analyzer. Process of getting informations from map file is explained in this chapter. Last chapter deal with benchmarks PARSEC and SPLAST. Two PARSEC programs are analysed here.

Conversion of Microsoft Word documents to the LaTeX format

Author
Jiří Anděl
Year
2013
Type
Master thesis
Supervisor
Ing. Jiří Kašpar
Reviewers
Mgr. Rudolf Bohumil Blažek, Ph.D.

Simulation of storage network configuration commands

Author
Karel Gudera
Year
2019
Type
Master thesis
Supervisor
Ing. Jiří Kašpar
Reviewers
Ing. Jan Trdlička, Ph.D.
Summary
This thesis deals with design and implementation of switch simulator which is based on Fibre Channel protocol. It is possible to start multiple instances of switch. Cascading of switches is implemented, i.e. switches can be interconnected by virtual links. These switches form a storage area network (fabric). Each switch has its own command line interface with which it can be configured, e.g. port configuration, alias configuration or zoning configuration. Furthermore, switches are able to simulate basic services that are used to connect and communicate with other devices such as storage, servers and moreover, a simulation coordinator which can partially control switches. All communication is realized by UDP datagrams. Emphasis is placed on the simulation of the command line interface rather than simulation of actual protocols.

Simulation of Cache Hierarchy and the MESIF Protocol

Author
Jan Kadlec
Year
2013
Type
Master thesis
Supervisor
Ing. Jiří Kašpar
Reviewers
doc. Ing. Ivan Šimeček, Ph.D.

Circular Queue Optimization

Author
Josef Kučera
Year
2017
Type
Master thesis
Supervisor
Ing. Jiří Kašpar
Reviewers
doc. Ing. Ivan Šimeček, Ph.D.
Summary
The purpose of this work is to outline and compare variants of implementation of circular queue CQ in language C for multiple writers and readers with concurrent access using locks and atomic operations on x86-64. Next, design a set of optimizations for inserting and retrieving messages from a circular queue and measure their performance by varying parameters such as length of the queue, message size, message processing, number of writers and readers and their deployment on processor cores.