Bachelor theses
Simulator of the 32-bit MIPS processor
Author
Ondřej Marek
Year
2019
Type
Bachelor thesis
Supervisor
Ing. Michal Štepanovský, Ph.D.
Reviewers
Ing. Jiří Kašpar
Department
Summary
This thesis deals with analysis, design and implementation of a system which allows to simulate running programs for target microarchitecture. Research part of the thesis deals with comparing of existing solutions and describes technologies and terms used further in the thesis, the practical part follows the presentation of the program design, description of its parts and methods used during implementation. The chosen problem was solved by integration of the program with hardware simulator Icarus Verilog. There was created a system which supports simplified microarchitecture MIPS32 in the base with the possibility to configure further microarchitectures. The benefit of this thesis is that students of computer-driven subjects will understand the structure and operation of processors thanks to visualisation. In attachment on USB stick there is a program, source codes and a manual.
Simulator of the 32-bit MIPS processor
Author
Petr Nešpůrek
Year
2019
Type
Bachelor thesis
Supervisor
Ing. Michal Štepanovský, Ph.D.
Reviewers
Ing. Zdeněk Buk, Ph.D.
Department
Summary
Goal of this work is to implement a processor simulator with MIPS32 instruction set. I will implement this as two programs - a simulator core written in Verilog hardware definition language and a GUI application written in Java with usage of graphic framework JavaFX. Result of this work is an application that reads and runs a program written in MIPS32 machine code and shows history of the program run. It displays values in processor modules and wires, data memory, instruction memory and cache simulation. This simulator will be used in BI-APS (Architectures of Computer Systems) course, instruction set is modified for needs of this course.
Analysis of the ZombieLoad attack
Author
Michal Převrátil
Year
2020
Type
Bachelor thesis
Supervisor
Ing. Michal Štepanovský, Ph.D.
Reviewers
Ing. Jiří Buček, Ph.D.
Department
Summary
The goal of this thesis is to describe a principle of the ZombieLoad attack and to perform it. The theoretical part introduces some specifics of modern processors. After that follows an analysis of the attack which includes a description of a cache side-channel. The theoretical part concludes with a chapter describing mitigations applied by operating systems and processors. The practical part describes the implementation of five variants of the attack on the Linux operating system. The description also includes any obstacles that can be encountered during an attack attempt and their solutions. The last chapter analyses the success rate of the implemented variants and abusement of vulnerabilities.
Secret communication using steganography
Author
Ondřej Voronecký
Year
2020
Type
Bachelor thesis
Supervisor
Ing. Michal Štepanovský, Ph.D.
Reviewers
Ing. Josef Kokeš
Department
Summary
This thesis focuses on the steganography, specificaly hiding any data into the
provided image, using error-correcting codes. The thesis analyzes the methods
of hiding data, various types of error-correcting codes and their capabilities to
extract the hidden data from the damaged (or modified) image. Based on this,
an application for hidding the given data into the image is created, including
a user interface. This application allows to select the error-correcting code
and embedding method to be used. With the help of created application, the
error-correcting codes and embedding methods are practicaly analysed. The
application was created and tested for the GNU/Linux operating system.
Analysis of the Fallout attack
Author
Radek Jizba
Year
2020
Type
Bachelor thesis
Supervisor
Ing. Michal Štepanovský, Ph.D.
Reviewers
Ing. Jiří Dostál, Ph.D.
Department
Summary
The aim of this thesis is to test the feasibility of Fallout exploit which
targets vulnerability of processor architectures and belongs to a group of
exploits known as MDS. Its theoretical part identifies the prerequisites
necessary to successfully use this exploit and subsequently analyses its
feasibility and impact. A program designed to detect weak spots in
operating systems and processor architecture was coded as a part of the
implemenation part of the thesis. Its purpose is to verify if incorrect
data can be forwarded to processing without prior check or alternatively if
the process should have access to the data in question. The included
program does not utilize any TSX instructions and hence can be used on
processors which do not support this extension.
Software for the age estimation based on the 3D scan of a pelvic bone
Author
Natália Pohanková
Year
2021
Type
Bachelor thesis
Supervisor
Ing. Michal Štepanovský, Ph.D.
Reviewers
Ing. Mgr. Pavla Vozárová, Ph.D., M.A.
Department
Summary
This bachelor thesis describes the process of development of a software application used to estimate the age of an adult based on a scan of his pelvis bone. Machine learning algorithms are currently being widely used in various fields including in forensic anthropology, paleontology and history. Using this software will make their part of the job focusing on age estimation significantly easier. In this thesis I focus on the analysis of input data, design of multiple machine learning models, which are used to estimate the age of individuals, their subsequent validation and lastly on the implementation and testing of the user interface.
Linux kernel vulnerabilities
Author
Jan Pánov
Year
2021
Type
Bachelor thesis
Supervisor
Ing. Michal Štepanovský, Ph.D.
Reviewers
doc. RNDr. Ing. Petr Zemánek, CSc.
Department
Summary
This thesis focuses on Linux kernel vulnerability CVE-2019-9213, which relates with a bug on Memory Management subsystem on Linux operating system. It allows mapping of vitual address 0. This vulnerability with Mutagen Astronomy and Dirty COW are analyzed and an attack is design in order to gain privilege escalation. On address 0 is stored a malicious code and is run in privileged mode. The attack is successfull however some system's protections are disabled.
Age-at-death estimation using machine learning methods
Author
Alexandr Czerný
Year
2023
Type
Bachelor thesis
Supervisor
Ing. Michal Štepanovský, Ph.D.
Reviewers
Ing. Jitka Hrabáková, Ph.D.
Department
Summary
Age at death estimation is one of the main tasks when creating biological profile in forensic anthropology. Skeletal remains are used for the estimation. Acetabulum is currently at the forefront of research interest. This thesis focuses on age at death estimation from acetabulum images using convolutional neural networks. In addition, emphasis is placed on input data preprocessing and hyperparameters tuning of selected model. The result of this thesis is a regression machine learning model for age at death estimation using acetabulum scans.
Vulnerabilities of modern processors
Author
Matyáš Černý
Year
2022
Type
Bachelor thesis
Supervisor
Ing. Michal Štepanovský, Ph.D.
Reviewers
Ing. Jiří Kašpar
Department
Summary
This bachelor's thesis is dedicated to research of select security vulnerabilities in modern processors. The theoretical portion contains a summary of the Rogue In-Flight Data Load, Load Value Injection and Foreshadow vulnerabilities. A more comprehensive description of the Lazy FP State Restore vulnerability is given including theoretical attack concepts. I present an attempt at implementing this attack which aims to leak a limited amount of another program's private data stored in CPU registers. I describe portions of the implementation source code which form the fundamentals of the attack. Findings made while creating the implementation and analysis of the prerequisites of this attack lead to the conclusion that LazyFP is not a severe security threat at this time.
Problems of elastic optical networks
Author
David Zeman
Year
2022
Type
Bachelor thesis
Supervisor
Ing. Michal Štepanovský, Ph.D.
Reviewers
RNDr. Ing. Vladimír Smotlacha, Ph.D.
Department
Summary
The main content of this bachelor thesis is the study of problems of elastic optical networks and their theoretical solutions. The optical fibers as a whole, their distribution and their properties are presented here. In my work I also focus on the comparison of elastic optical networks with dense wave multiplexing "DWDM". This comparison part is to find out what volume of spectrum and under what conditions newer technology can save. The contribution of the work is also a detailed presentation of the RSA problem, which discusses the main functions of optical fibers, namely routing and spectrum allocation.
However, there are many problems associated with this, such as spectrum fragmentation, signal modulation and others, which are also presented in this work. At the end of the work I deal in more detail with the problem of error resistance, which I analyzed in detail.
RISC-V CPU superscalar microarchitecture design
Author
Tomáš Věžník
Year
2023
Type
Bachelor thesis
Supervisor
Ing. Michal Štepanovský, Ph.D.
Reviewers
doc. Ing. Ivan Šimeček, Ph.D.
Department
Summary
This thesis aims to explain the superscalar processor's working principles and to design a microarchitecture based on the RISC-V RV32I instruction set architecture. The designed microarchitecture is called VTM (Veznik Tomas Microarchitecture) and is described using SystemVerilog hardware description language. The VTM is a dual-issue out-of-order superscalar microarchitecture that executes up to four instructions in the execution stage simultaneously. The primary output of this thesis is the VTM source code. The simulation, accompanied by the theoretical part of this thesis, serves as a learning tool for anyone who wants to understand the inner workings of superscalar processors, with students as the primary audience.
Implementation of superscalar microarchitecture in HDL
Author
Aleksei Egorov
Year
2024
Type
Bachelor thesis
Supervisor
Ing. Michal Štepanovský, Ph.D.
Reviewers
Ing. Jan Bělohoubek, Ph.D.
Department
Summary
This bachelor's thesis is devoted to studying the principles of superscalar processor architectures and designing my own architecture based on ISA RISC-V RV32I, describing it in HDL. The designed CPU is ideally able to read from memory 2 instructions at once and finish also 2 instructions at once. The source codes written in Verilog can be used as a basis for future undergraduate theses or used in teaching.
Branch prediction in superscalar microarchitecture
Author
Štěpán Šebek
Year
2025
Type
Bachelor thesis
Supervisor
Ing. Michal Štepanovský, Ph.D.
Reviewers
Ing. Matej Hulák
Department
Summary
The work focuses on branch predictors, an essential part of modern superscalar processors. First, the role of branch predictors in superscalar processors and several existing designs is discussed. A total of 6 discussed branch direction predictor designs are implemented in the Verilog hardware description language. Subsequently, the necessary tools for simulation are designed and implemented. Verification simulations and simulations of 8 different real programs are performed. At the end of the work, simulation data is evaluated in terms of prediction accuracy, and interesting behaviour of specific programs on specific predictors is discussed; the simulation also confirms the functionality of the implementations.
Process scheduling in operating systems with regard to security
Author
Martin Pelíšek
Year
2025
Type
Bachelor thesis
Supervisor
Ing. Michal Štepanovský, Ph.D.
Reviewers
Ing. Martin Šutovský
Department
Summary
This bachelors thesis focuses on process scheduling in operating systems, emphasizing
both performance and security aspects. It begins with a systematic
overview of key scheduling algorithms FCFS, SJF, RR, Priority Scheduling,
MLQ and MLFQ analyzing their advantages, disadvantages, and potential
vulnerabilities. The thesis also includes a study of scheduling mechanisms
in Windows and Linux, including an analysis of how these systems address
security aspects of scheduling. The practical outcome is a custom simulator
of scheduling algorithms supporting multicore systems, blocking operations,
and interactive visualization of the simulation process using a Gantt chart.
The experimental analysis evaluates the performance of individual algorithms
and demonstrates the mitigation of starvation and manipulation of priority
queues within a basic MLFQ implementation.
Master theses
RISC-V open-source microarchitecture analysis and optimization
Author
Ondřej Golasowski
Year
2025
Type
Master thesis
Supervisor
Ing. Michal Štepanovský, Ph.D.
Reviewers
Ing. Stanislav Jeřábek, Ph.D.
Department
Summary
This master's thesis focuses on the soft-processor and system on chip (SoC) design. The processor is based on the extension of a RISC-V processor microarchitecture. The aim is to analyze and implement features that enable practical use of the soft-processor, while maintaining the simplicity of the original microarchitecture. This property is crucial for applications in computer architecture courses.
The outcome of the thesis is a processor with a single-cycle microarchitecture supporting the RV32IMZicsr instruction set, the Machine Mode privileged level, and debugging via the GNU Debugger tool according to the official specification. The processor operates at a clock frequency of 50 MHz and uses the Wishbone system bus. As part of the work, a system on chip was also developed, integrating the designed processor and a wide range of peripherals, including 512 KiB of system RAM, an HDMI audio-video adapter, a serial port, general-purpose inputs and outputs, a debugging module, and other components. The system is synthesizable for the Nexys Video FPGA platform and includes a complete simulation setup with support for a virtual JTAG interface. Both synthesis and simulation are managed by a unified configuration tool, which works as a user-friendly front-end for underlying electronic design automation (EDA) tools.
The thesis also includes software support in the form of a C language Software Development Kit (SDK). The SDK provides both low-level and high-level drivers for peripherals. The use of the SDK is illustrated through sample applications, such as a music player.
The overall system design was conceived with a strong emphasis on simplicity and clarity, making it a suitable tool for educational purposes.
Implementation of RISC-V soft-core processor on FPGA board with real-time operating system support
Author
Jan Medek
Year
2025
Type
Master thesis
Supervisor
Ing. Michal Štepanovský, Ph.D.
Reviewers
Ing. Pavel Píša, Ph.D.
Department
Summary
The goal of this thesis is to implement a small computer system based on an FPGA and to develop support for a selected real-time operating system. The first part of the thesis analyzes several open-source real-time operating systems that support the RISC-V architecture, as well as several open-source RISC-V soft processors, together with systems that integrate these processors and connect them to peripherals. The result of this analysis is the selection of NuttX, a highly configurable and modular operating system that supports the POSIX interface and incorporates many concepts from other Unix operating systems, and the selection of a soft system called Ibex Demo System, integrating a small 32-bit RISC-V soft processor called Ibex, memory, a RISC-V compatible debug module, and several basic peripherals for external communication. The second part of the thesis describes their integration into one functional computer system. Ibex Demo System is first adapted to run on the Basys 3 and Nexys Video FPGA boards, and its UART module is extended. Furthermore, NuttX is ported to Ibex Demo System, with support added for both of the mentioned FPGA boards. In both cases, configurations are created for existing applications to demonstrate the functionality of the developed computer system. The result of the work is a transparent computer system whose operation can be monitored at the system level using the traditional tool GDB, making it ideal for educational purposes as well.