Device for integrated and distributed control and management of intelligent buildings and flats
Date of granting patent
29. 11. 2017
Applicant
<p>Czech Technical University in Prague, Faculty of Electrical Engineering</p>
Types of industrial property
<p>Czech national patent</p>
Information by the IPO
<p><a data-tabindex-counter="4" data-tabindex-value="none" href="https://isdv.upv.cz/webapp/resdb.print_detail.det?pspis=PT/2014-260&plang=CS" target="_blank">Device for integrated and distributed control and management of intelligent buildings and flats</a></p>
Documents
<p><a data-tabindex-counter="4" data-tabindex-value="none" href="http://isdv.upv.cz/doc/FullFiles/Patents/FullDocuments/307/307094.pdf" target="_blank">Specification of the patent no. 307 094</a></p>
No. of application
2014-260
No. of document
307 094
Date of application submission
15. 4. 2014
Date of granting patent
29. 11. 2017
Date of patent publication
10. 1. 2018
Annotation
<p>The device represents an effective solution for intelligent buildings and flats. It is based on IP/PLC communication protocols and provides management and control using network distribution cabling. The centre of the device is a microcomputer (1) communicating with other devices of this type and with the Internet via a communication module (2) and a frequency filter (3). The module (4) of the switching elements is controlled by the phase conductor (L) of the connected network elements, while the module (5) for measuring the currents flowing into the neutral conductor (N) provides information on their consumption. The module (6) for sensing the state of the control elements allows connection of a driver, such as switches, buttons or potentiometers of the network distribution cabling. The source (7) powers the device and its accumulator supports the basic functions at network outages. The input/output interface (8) allows connection of various sensors, camera sensors, memory elements and wireless modules. The data can be processed locally, in collaboration with other elements according to the design, and/or distributed to the Internet. The device can be connected to an RS-485 bus used in standard building and flat control networks using a converter (9).<img pimcore_disable_thumbnail="true" pimcore_id="261" pimcore_type="asset" src="/veda-a-vyzkum/patenty/patent307094.jpg" style="width:413px;" /></p>
System for implementation of a dispersion table
Date of granting patent
24. 5. 2017
Applicant
<p>CESNET, z. s. p. o.<br />
Czech Technical University in Prague, Faculty of Information Technology</p>
Types of industrial property
<p>Czech national patent<br />
European patent<br />
United States Patent</p>
Information by the IPO
<p><a data-tabindex-counter="9" data-tabindex-value="none" href="https://isdv.upv.cz/webapp/resdb.print_detail.det?pspis=PT/2016-272&plang=CS" target="_blank">IPO: System for implementation of a dispersion table</a><br />
<a data-tabindex-counter="9" data-tabindex-value="none" href="https://worldwide.espacenet.com/publicationDetails/biblio?DB=EPODOC&II=0&ND=3&adjacent=true&locale=en_EP&FT=D&date=20171115&CC=EP&NR=3244324A1&KC=A1" tabindex="-1" target="_blank">Espacenet: System for Implementation of a Hash Table</a><br />
<a data-tabindex-counter="9" data-tabindex-value="none" href="/veda-a-vyzkum/patenty/patent306787_us.pdf" pimcore_id="260" pimcore_type="asset" target="_blank">United States Patent: System for Implementation of a Hash Table</a></p>
Documents
<p><a data-tabindex-counter="9" data-tabindex-value="none" href="http://spisy.upv.cz/Patents/FullDocuments/306/306787.pdf" target="_blank">Specification of the patent no. 306 787</a></p>
No. of application
2016-272
No. of document
306 787
Date of application submission
10. 5. 2016
Date of granting patent
24. 5. 2017
Date of patent publication
7. 7. 2017
Annotation
<p>The solution submitted enables implementation of a dispersion table, for example for compression algorithms, with fast initialization and, at the same time, small demands on system resources. The main parts of the solution are one or more base blocks (1), a corresponding number of masking blocks (20), the counter (14), the address divider (15), the demultiplexer (18) and the multiplexer (22). Each base block (1) includes the flag register memory (4) implemented as a LUT table. In the normal operating mode, the address of the entire symptom system is divided by the address divider (15) into a part connected simultaneously to all the base blocks (1) and to a part that the demultiplexer (18) uses to enable writing in one of the base blocks (1). The masking blocks (20) together with the multiplexer (22) select the contents of the addressed base block (1). In the initialization mode, the counter (14) successively creates all the addresses on the base block (1) inputs for setting the flag register memory (4).<img pimcore_disable_thumbnail="true" pimcore_id="262" pimcore_type="asset" src="/veda-a-vyzkum/patenty/patent306787.jpg" style="width:413px;" /></p>
Circuit arrangement for integrated control and management in service networks of smart buildings
Date of granting patent
9. 10. 2013
Applicant
<p>Czech Technical University in Prague, Faculty of Electrical Engineering</p>
Types of industrial property
<p>Czech national patent<br />
Deutsches Patent</p>
Information by the IPO
<p><a data-tabindex-counter="5" data-tabindex-value="none" href="https://isdv.upv.cz/webapp/resdb.print_detail.det?pspis=PT/2012-685&plang=CS" target="_blank">Circuit arrangement for integrated control and management in service networks of smart buildings</a></p>
Documents
<p><a data-tabindex-counter="5" data-tabindex-value="none" href="http://spisy.upv.cz/Patents/FullDocuments/304/304151.pdf" target="_blank">Specification of the patent no. 304 151</a></p>
No. of application
2012-685
No. of document
304 151
Date of application submission
9. 10. 2012
Date of granting patent
9. 10. 2013
Date of patent publication
20. 11. 2013
Annotation
<p>The present invention covers a device for efficient solution and project of service network of smart buildings, which is based on sharing a harness that is primary used for making local computer networks of Ethernet, i.e. four-pair cables UTP Cat.5, optionally Cat.6. The device comprises a central processor (1), which supports any program needful for the device function. Interface (2) 802.3 for communication by IEEE 802.3c protocol interconnects the device with two pairs (1-2 a 3-6) of the UTP cable normally used by the Ethernet technology. Interface (3) of the RS-485 bus uses in common Ethernet local networks and devices used therein such as routers, switches, servers, memory centers, printers, and other unused pairs (5-4) of the UTP cables as a bus complying with the standard RS-485 in the synchronous communication (peer-to-peer) operational mode. The described device can also be provided with a suitable input/output module (4), making it possible to operate with optional own sensors or own control elements, and/or it can locally provide for the user information about the state and to ensure control of the device itself, as well as through the mediation of the central processor (1) and the IEEE 802.3 interface (2) for the communication through the protocol IEEE 802.3c and the interface (3) of the RS-485 bud of arbitrary other device of the service network, and/or it can serve for processing optical information of a camera sensor, i.e. to provide storage of data, its evaluation, for example detection of movement and its preparation for transmission to the central processor of the service network computer or to a remote indicator. A power supply unit (5) for other parts of the device uses the free pairs (7-8) of the UTP cables and makes it possible to feed sensors and control elements of the busses RS-485 as well as mutual backup of other devices. The connection of contacts between the interface (3) of the RS-485 bus and the two pairs (1-2) and (3-6) makes it possible to use the cables connected to connectors (B, C) of the RJ-45 type and unused for Ethernet transmission for additional bus according to RS-485 in the asynchronous communication mode of operation.</p>
<p><img pimcore_disable_thumbnail="true" pimcore_id="263" pimcore_type="asset" src="/veda-a-vyzkum/patenty/patent304151.jpg" style="width:413px;" /></p>
Circuit arrangement for generating multiplicative inversion above final GF (p) body
Date of granting patent
7. 2. 2005
Applicant
<p>Czech Technical University in Prague, Faculty of Electrical Engineering</p>
Types of industrial property
<p>Czech national patent<br />
United States Patent 7574469</p>
Information by the IPO
<p><a data-tabindex-counter="5" data-tabindex-value="none" href="https://isdv.upv.cz/webapp/resdb.print_detail.det?pspis=PT/2002-4116&plang=CS" target="_blank">Circuit arrangement for generating multiplicative inversion above final GF (p) body</a></p>
Documents
<p><a data-tabindex-counter="5" data-tabindex-value="none" href="http://spisy.upv.cz/Patents/FullDocuments/294/294898.pdf" target="_blank">Specification of the patent no. 294 898</a></p>
No. of application
2002-4116
No. of document
294 898
Date of application submission
16. 12. 2002
Date of granting patent
7. 2. 2005
Date of patent publication
13. 4. 2005
Annotation
<p>In the present invention, there is disclosed a circuit arrangement for generating efficient multiplicative inversion above final GF (p) body wherein p represents a prime number, i.e. by generating modular inversion. The circuit is adapted to carry out operations by binary way within the process of generation of the modular inversion relative to the least possible number of addition, subtraction and shift operations. The process implemented by the circuit here proposed removes redundant operations after conversion of odd and negative values that are carried out in so far employed processes. For this purpose there is used a representation of negative numbers in an additional code, shift of values to left in the control section of Euclid algorithm and novel definition of monitoring and control conditions serving for execution of the process. Minimizing the number of adding and subtracting operations is desirable in case of calculation with large numbers that occur in cryptography.</p>
<p><img pimcore_id="264" pimcore_type="asset" src="/veda-a-vyzkum/patenty/264/image-thumb__264___auto_4ff316290744e96cb430c8786d768fbe/patent294898.0c92e106.jpg" srcset="/veda-a-vyzkum/patenty/264/image-thumb__264___auto_4ff316290744e96cb430c8786d768fbe/patent294898.0c92e106.jpg 1x, /veda-a-vyzkum/patenty/264/image-thumb__264___auto_4ff316290744e96cb430c8786d768fbe/patent294898@2x.0c92e106.jpg 2x" srcset="/veda-a-vyzkum/patenty/264/image-thumb__264___auto_4ff316290744e96cb430c8786d768fbe/patent294898.0c92e106.jpg 1x, /veda-a-vyzkum/patenty/264/image-thumb__264___auto_4ff316290744e96cb430c8786d768fbe/patent294898@2x.0c92e106.jpg 2x" style="width:600px;" /></p>
Processor unit connection
Date of granting patent
30. 12. 1987
Applicant
<p>Institute of Physics CEFV SAS, Bratislava</p>
Types of industrial property
<p>Czechoslovak national patent</p>
Information by the IPO
<p><a data-tabindex-counter="3" data-tabindex-value="none" href="https://isdv.upv.cz/webapp/resdb.print_detail.det?pspis=PT/1986-5867&plang=CS" target="_blank">Processor unit connection</a></p>
Documents
<p><a data-tabindex-counter="3" data-tabindex-value="none" href="http://spisy.upv.cz/Patents/FullDocuments/257/257355.pdf">Specification of the patent no. 257 355</a></p>
No. of application
1986-5867
No. of document
257 355
Date of application submission
6. 8. 1986
Date of granting patent
30. 12. 1987
Date of patent publication
15. 12. 1988
Annotation
<p><img pimcore_id="265" pimcore_type="asset" src="/veda-a-vyzkum/patenty/265/image-thumb__265___auto_4ff316290744e96cb430c8786d768fbe/patent1987.c6f29886.jpg" srcset="/veda-a-vyzkum/patenty/265/image-thumb__265___auto_4ff316290744e96cb430c8786d768fbe/patent1987.c6f29886.jpg 1x, /veda-a-vyzkum/patenty/265/image-thumb__265___auto_4ff316290744e96cb430c8786d768fbe/patent1987@2x.c6f29886.jpg 2x" srcset="/veda-a-vyzkum/patenty/265/image-thumb__265___auto_4ff316290744e96cb430c8786d768fbe/patent1987.c6f29886.jpg 1x, /veda-a-vyzkum/patenty/265/image-thumb__265___auto_4ff316290744e96cb430c8786d768fbe/patent1987@2x.c6f29886.jpg 2x" style="width:600px;" /></p>