Projects

2022 - 2025

Projekt reaguje na současný nedostatek nástrojů pro analýzu a verifikaci bezpečnostní certifikace zařízení používaných pro zajištění kybernetické bezpečnosti. Zejména u hardwarových zařízení implementujících kryptografické algoritmy, například čipových karet, je v ČR téměř nemožné spolehlivě ověřit deklarovanou úroveň bezpečnosti, což následně znemožňuje analýzu rizik systémů využívajících tato zařízení a tedy použití zařízení např. u bezpečnostních složek státu či v rámci kritických informačních infrastruktur. V rámci projektu budou vyvinuty nové hardwarové a softwarové nástroje založené na principech umělé inteligence, které bude možné využít pro specifické kroky automatizované verifikace bezpečnosti kryptografického zařízení - ať už na základě bezpečnostní certifikace nebo tvrzení výrobce/dodavatele.

2020 - 2022

The project deals with the digital design focused on embedded systems. It will cover the study of the latest trends in technologies and their use in mission-critical applications. The design of such systems must take into account not only functionality but also other constraints; they must meet the required levels of reliability, security, attack resistance, size, power consumption, and real-time guarantees. Therefore, we will use new methods, algorithms and design tools (EDA tools) to find, design and modify suitable models that will allow to test, predict and formally verify the required functions and behavior of the system.

2017 - 2019

The Internet of Things (IoT) is increasingly becoming part of our everyday life. Therefore, electronic IoT devices need to be carefully designed, taking into account data security and privacy. Putting in place security and privacy measures should introduce a minimal overhead in the system's power/energy consumption, cost and operational delay. Additionally, since IoT devices are everywhere, attackers can be in the vicinity of the device, which stresses the need for protection against side-channel analysis (SCA) attacks. These attacks exploit the use of side-channels, which are information channels that are unintentionally present in electronic devices and which potentially leak secret information. Examples are the power consumption, the electromagnetic radiation and the timing behaviour of the electronic device. In both academia and industry, SCA countermeasures are being developed and deployed. However, as SCA attacks become more and more sophisticated, continuously evolving countermeasures are necessary to protect the electronic devices of the future. This project proposes the use of dynamic hardware reconfiguration as a countermeasure against one of the most exploited types of SCA attacks, namely power analysis attacks. The goal is to randomly change the hardware circuit without altering the input-output behaviour of the chip. Since power analysis attacks are strongly based on the knowledge of the circuit, this is a very promising countermeasure. Another advantage is that dynamic hardware reconfiguration can be used as an add-on to other countermeasures. The project focuses on dynamic hardware reconfiguration on FPGAs (field-programmable gate arrays). It will result in proof-of-concept implementations that will be evaluated for power analysis attack resistance. The experimental results are crucial for the definition of a European project proposal that develops an automated tool flow and industry-driven use cases to show the effectiveness of the approach.

2017 - 2019

This project proposal will study and design architectures which are able to tolerate faults, attacks, and unreliable sensory inputs especially in programmable devices (FPGAs), microcontroller systems and embedded systems with artificial intelligence integrated. This is typically achieved by introduction of redundancy by replicating critical circuits or by combining multiple sensory inputs. Security of devices, i.e., their resistance to malicious attacks, is the second extremely important aspect of today. Security is also often achieved by redundancy, aiming at obscuring data. The interaction between techniques for fault-tolerant, sensory robust and attack-resistant design will be studied. The intersection of all fields and the influence of controllability, observability, and redundancy will be studied.

2016 - 2018

With continuing miniaturization of present electronic devices, their dependability becomes significantly compromised. It is thus necessary to design devices that are reliable (functioning) even in presence of faults. This is typically achieved by introduction of redundancy, by which a correctness of data is ensured. Security of devices, i.e., their resistance to malicious attacks, is the second extremely important aspect of today. The security is also often achieved by redundancy, aiming at obscuring data. The interaction between techniques for fault-tolerant and attack-resistant design is however not well understood. The crossing points of both fields, the influence of controllability, observability, and redundancy will be studied. The target architecture will be programmable devices (FPGAs). It is necessary to devise a realistic fault model in FPGA for evaluation purposes. The model will be refined by calibrations using accelerated life tests (ALT).