Optically induced static power in combinational logic: Vulnerabilities and countermeasures

Year
2021
Published
Microelectronics Reliability. 2021, 124 ISSN 0026-2714.
Type
Article
Annotation
Physical attacks, namely invasive, observation, and combined, represent a great challenge for today's digital design. Successful class of strategies adopted by industry, allowing hiding data dependency of the side channel emissions in CMOS is based on balancing. Although attacks on CMOS dynamic power represent a class of state-of-the-art attacks, vulnerabilities exploiting data dependency in CMOS static power and light-modulated static power were recently presented. In this paper, we describe structures and techniques developed to enhance and balance the power imprint of the traditional static CMOS bulk structures under invasive light attack. The novel standard cells designed according to the presented techniques in the TSMC180nm technology node were used to synthesize the dual-rail AES SBOX block. The behavior of the AES SBOX block composed of the novel cells is compared to classical approaches. Usage of novel cells enhances circuit security under invasive light attack while preserving comparable circuit resistance against state-of-the-art power attacks.

Emerging Technologies: Challenges and Opportunities for Logic Synthesis

Authors
Bosio, A.; Cantan, M.; Marchand, C.; O'Connor, I.; Fišer, P.; Poittevin, A.; Traiola, M.
Year
2021
Published
Proceedings of 24th International Symposium on Design and Diagnostics of Electronic Circuits and Systems. Piscataway (New Jersey): IEEE, 2021. p. 93-98. ISBN 978-1-6654-3595-6.
Type
Proceedings paper
Annotation
In computer engineering, logic synthesis is a process by which an abstract specification of desired circuit behavior is turned into a design implementation in terms of logic gates. Historically, logic synthesis was tightly related to the physical implementation of the logic gates. Nowadays, pushed by the forecasted end of Moore's law, several emerging technologies (e.g., nanodevices, optical computing, quantum computing) are candidates to either replace or co-exist with the \textit{de facto} standard CMOS technology. The main consequence of the rising of those emerging technologies is that the logic synthesis has to face new issues and, at the same time, exploits new opportunities. The goal of this paper is thus to present three emerging technologies (Vertical Nanowire Field Effect Transistors, Ferroelectric Transistors, and Memristors), how to use them to implement logic gates, and the main challenges and issues for the logic synthesis.

Side-channel attack on Rainbow post-quantum signature

Authors
Pokorný, D.; Socha, P.; Novotný, M.
Year
2021
Published
Proceedings of the 2021 Design, Automation & Test in Europe (DATE). New Jersey: IEEE, 2021. p. 565-568. ISSN 1558-1101. ISBN 978-3-9819263-5-4.
Type
Proceedings paper
Annotation
Rainbow, a layered multivariate quadratic digital signature, is a candidate for standardization in a competition-like process organized by NIST. In this paper, we present a CPA side-channel attack on the submitted 32-bit reference implementation. We evaluate the attack on an STM32F3 ARM microcontroller,successfully revealing the full private key. Furthermore, we propose a simple masking scheme with minimum overhead.

Towards Evaluating Quality of Datasets for Network Traffic Domain

Authors
Soukup, D.; Tisovčík, P.; Hynek, K.; Čejka, T.
Year
2021
Published
Proceedings of the 2021 17th International Conference on Network and Service Management. New York: IEEE, 2021. p. 264-268. ISSN 2165-963X. ISBN 978-3-903176-36-2.
Type
Proceedings paper
Annotation
This paper deals with the quality of network traffic datasets created to train and validate machine learning classification and detection methods. Naturally, there is a long epoch of research targeted at data quality; however, it is focused mainly on data consistency, validity, precision, and other metrics, which are insufficient for network traffic use-cases. The rise of Machine learning usage in network monitoring applications requires a new methodology for evaluation datasets. There is a need to evaluate and compare traffic samples captured at different conditions and decide the usability of the already captured and annotated data. This paper aims to explain a use case of dataset creation, propose definitions regarding the quality of the network traffic datasets, and finally, describe a framework for datasets analysis.

Secure and dependable: Area-efficient masked and fault-tolerant architectures

Year
2021
Published
Proceedings of the 2021 24th Euromicro Conference on Digital System Design. Los Alamitos: IEEE Computer Society, 2021. p. 333-338. ISBN 978-1-6654-2703-6.
Type
Proceedings paper
Annotation
Masking is a powerful instrument for protecting cryptographic devices against side-channel analysis. Multiple masking schemes were introduced providing provable security against attacks of arbitrary order even in the presence of glitches. When a device is a part of some safety-critical system, it needs to meet dependability requirements; therefore, it should be protected against spontaneously occurring faults. Existing commonly used fault-tolerance architectures involve high area overhead as so as the masking schemes do. In this paper, we propose architectures meeting dependability properties of simple modular-redundancy schemes and SCA resistance of masking schemes, but decreasing the area overhead utilizing the randomness involved in the masking schemes. We compare our Masked Duplex architecture with Triple Modular Redundancy. While using one less redundant module, our architecture saves around 20% of the area in comparison with TMR in the case of Threshold Implementation of PRESENT cipher, promising more savings for more complex cryptographic schemes

Privacy Illusion: Beware of Unpadded DoH

Year
2020
Published
2020 11th IEEE Annual Information Technology, Electronics and Mobile Communication Conference (IEMCON). Montreal: IEEE, 2020. p. 621-628. ISSN 2644-3163. ISBN 978-1-7281-8416-6.
Type
Invited/Awarded proceedings paper
Annotation
DNS over HTTPS (DoH) has been created with ambitions to improve the privacy of users on the internet. Domain names that are being resolved by DoH are transferred via an encrypted channel, ensures nobody should be able to read the content. However, even though the communication is encrypted, we show that it still leaks some private information, which can be misused. Therefore, this paper studies the behavior of the DoH protocol implementation in Firefox and Chrome web-browsers, and the level of detail that can be revealed by observing and analyzing packet-level information. The aim of this paper is to evaluate and highlight discovered privacy weaknesses hidden in DoH. By the trained machine learning classifier, it is possible to infer individual domain names only from the captured encrypted DoH connection. The resulting trained classifier can infer domain name from encrypted DNS traffic with surprisingly high accuracy up to 90% on HTTP 1.1, and up to 70% on HTTP 2 protocol.

Automatic Test Pattern Generation of Zero-Aliasing Test for General Output Response Compactor

Author
Ing. Robert Hülle
Year
2023
Type
Dissertation thesis
Supervisor
doc. Ing. Petr Fišer, Ph.D.
Reviewers
Assoc. Prof. Paolo Bernardi, PhD.
Dr. Stephan Eggersgluess
Prof. Liviu-Cristian Miclea, PhD.

The Impact of Encrypted DNS on Network Security

Author
Ing. Karel Hynek
Year
2023
Type
Dissertation thesis
Supervisor
prof. Ing. Hana Kubátová, CSc.
Reviewers
RNDr. Tomáš Jirsík, Ph.D.
prof. Rémi Badonnel, Ph.D.
prof. Ramin Sadre, Ph.D.

Object detection in protected area using dToF sensors in automotive environment

Author
Petr Moucha
Year
2023
Type
Master thesis
Supervisor
Ing. Jiří Andrle
Reviewers
Dr.-Ing. Martin Novotný
Summary
This work describes the implementation of a device that aims to guard a defined area inside a car against the intrusion of unwanted objects. The protected area is covered with direct Time-of-Flight (dToF) sensors from STMicroelectronics, which are qualified for automotive applications. The device has been designed from the ground up to be a self-contained unit that includes not only the protected area itself but also all the electronics needed to read the sensor data and evaluate the presence of objects. The basic detection algorithm has been implemented on a PowerPC microcontroller and its results are signaled in real time by an LED. All integrated circuits and other electrical components were soldered on custom PCBs designed specifically for this thesis. The device can optionally be connected via USB cable to a desktop user interface that can graphically represent the sensor data, but in addition, it also allowed for easier development of a more advanced version of the detection algorithm. This external variant was also used for final testing, which showed that the system could correctly respond to the presence of most spatially significant objects, but for example a coin and other objects with low reflectivity could not be reliably detected over the entire protected area. Several external factors were also discovered that further negatively affect the algorithm and should be taken into account in future versions.

Integration of the safety certified PXROS-HR real-time operating system in ROS2 robotic system.

Author
Jakub Zahradník
Year
2023
Type
Master thesis
Supervisor
Ing. Martin Daňhel, Ph.D.
Reviewers
Ing. Roman Knížek
Summary
This master's thesis provides a comprehensive analysis of the Robot Operating System (ROS) 2, including its architecture, communication patterns, concepts, and use of the Data Distribution Service (DDS) as a middleware for data sharing. Additionally, the thesis explores Micro-ROS, a lightweight version of ROS 2 designed to run on microcontrollers with limited resources. This work focuses on analyzing the Micro-ROS's architecture, features, and suitability for embedded systems use. Additionally, the thesis explores using PXROS-HR, a real-time operating system (RTOS), in the proposed solution. The proposed solution involves building a custom static library for Micro-ROS and implementing a mutex task for thread-safe data access. The project structure is presented, including configurations and linker files, and describes the implementation of custom allocators and custom transport for Micro-ROS. The thesis also includes demonstrations of multithread publisher-subscriber and multicore publisher-subscriber for Micro-ROS, showcasing the proposed solution's feasibility and effectiveness. Furthermore, the proposed solution is evaluated by conducting one test for each demo, including publishing and subscribing to a topic, creating a service server for remote procedures, and distributing work to multiple tasks or cores. The results demonstrate that the proposed solution achieves thread-safe data access and enables efficient communication in resource-constrained environments.

Design of System On Chip with RISC-V processor for USI graphical pen controller

Author
Martin Stahl
Year
2023
Type
Master thesis
Supervisor
Ing. Tomáš Novák
Reviewers
Dr.-Ing. Martin Novotný
Summary
This diploma thesis covers the RTL design and implementation of System On Chip based on the RISC-V processor platform for USI graphical pen controller. The current CoolRISC-based pen controller SoC is analysed and based on this analysis new system design for the RISC-V-based pen controller SoC is created. The RTL design of the new SoC is implemented into 180\,nm technology, and its system power consumption is measured in simulation and then compared to the existing CoolRISC-based system. The thesis also covers the technical comparison between CoolRISC and RISC-V processor platforms.

Nintendo Entertainment System Emulation

Author
Ondřej Golasowski
Year
2023
Type
Bachelor thesis
Supervisor
Ing. Stanislav Jeřábek
Reviewers
Ing. Michal Štepanovský, Ph.D.
Summary
The bachelor's thesis is focused on the problematics of software emulation in the context of teaching the principles of computer architectures and associated hardware. There is a whole emulator development process presented in an example of a particular computer system, which is the Nintendo Entertainment System. The process consists of understanding the basic principles behind software emulation, analysis of the emulated system, design of the solution based on discovered information, and finally, the implementation of the emulator including testing. The goal of the implementation is to be as comprehensible as possible. The project also includes a universal platform for emulator development. To motivate other students (or hobbyists) interested in the topic, there is a list of possible extensions of the project in the last chapter of the thesis. Detailed documentation was created to make the project more accessible for emulator developers and potential project contributors.

Camera device for remote space monitoring using ESP32-CAM and SIM800L modules

Author
Adam Staes
Year
2023
Type
Bachelor thesis
Supervisor
Ing. Pavel Kubalík, Ph.D.
Reviewers
Ing. Vojtěch Miškovský, Ph.D.
Summary
The bachelor thesis deals with the design and creation of a camera device for remote space monitoring using ESP32-CAM and SIM800L modules. Existing solutions are explored in the work and a custom solution is proposed. The result of this work is a device capable of detecting motion and taking a picture of the monitored space. The image is stored on an SD card and sent via mobile data to the user's email address. The user can control the device with commands via SMS. A printed circuit board and a 3D printable enclosure are designed for the device.

RISC-V CPU superscalar microarchitecture design

Author
Tomáš Věžník
Year
2023
Type
Bachelor thesis
Supervisor
Ing. Michal Štepanovský, Ph.D.
Reviewers
doc. Ing. Ivan Šimeček, Ph.D.
Summary
This thesis aims to explain the superscalar processor's working principles and to design a microarchitecture based on the RISC-V RV32I instruction set architecture. The designed microarchitecture is called VTM (Veznik Tomas Microarchitecture) and is described using SystemVerilog hardware description language. The VTM is a dual-issue out-of-order superscalar microarchitecture that executes up to four instructions in the execution stage simultaneously. The primary output of this thesis is the VTM source code. The simulation, accompanied by the theoretical part of this thesis, serves as a learning tool for anyone who wants to understand the inner workings of superscalar processors, with students as the primary audience.

Robot Pepper Application for Mobile Phone Operator

Author
Adam Švehla
Year
2022
Type
Bachelor thesis
Supervisor
Ing. Miroslav Skrbek, Ph.D.
Reviewers
Ing. Zdeněk Buk, Ph.D.
Summary
This bachelor thesis covers the design and implementation of an application for the Pepper humanoid robot, which is aimed at supporting customer care at a mobile phone operator's branch office. The work analyzes the available technologies for the needs of the application and at the same time tries to avoid shortcomings and errors of similar solutions. The aim of the work is to implement an interactive application that will inform and entertain customers. The result is a robust solution that uses state-of-the-art cloud technology for speech recognition and artificial intelligence for localization and intent detection, which stands out in terms of communication, user-friendliness and user experience.

Implementation of Paillier cryptosystem & fault-injection attack on CEC 1702 processor

Author
Lukáš Daněk
Year
2022
Type
Bachelor thesis
Supervisor
Dr.-Ing. Martin Novotný
Reviewers
Ing. Jakub Klemsa
Summary
The bachelor thesis focuses on working with the CEC1702 cryptoprocessor. The first part of the thesis is oriented on programming the cryptoprocessor, modification of existing implementation of the library for operating on large numbers, and implementation of the Paillier cryptosystem for the mentioned cryptoprocessor. The thesis also includes development of firmware that allows the use of the RSA-CRT encryption algorithm and the Paillier cryptosystem with variable key length. The second part of the thesis focuses on fault injection attacks on the RSA-CRT encryption algorithm. Power supply glitches and clock source glitches used are generated using the ChipWhisperer suite. The attacks are first successfully performed on the STM32F3 microcontroller, where RSA-CRT is implemented using the library for operating on large numbers from the first part of the thesis. Using the knowledge from the attacks on the STM32F3, a further set of attacks was designed for the CEC1702 cryptoprocessor, using only power supply glitches, as the CEC1702 does not have the ability to use an external clock source. The attack was performed on two versions of RSA-CRT. The first version corresponds to the implementation for the STM32F3. The second version uses a hardware accelerator for cryptographic operations. The attack was successful on both versions of the implementation. This thesis outlines a possible approach to extend the created implementations and the implemented fault injection attacks. Created manual for programming the cryptoprocessor and the firmware documentation can be found in the appendix of the thesis.

Software for Nixie clock

Author
Martina Bechyňová
Year
2022
Type
Bachelor thesis
Supervisor
Ing. Matěj Bartík, Ph.D.
Reviewers
doc. Ing. Ivan Šimeček, Ph.D.
Summary
The aim of this thesis is to create control software for a custom-made embedded system using an STM32WB microcontroller unit that can be configured via Bluetooth Low Energy (BLE). The thesis concerns itself with analyzing the criteria placed on the software and the development of said software. The thesis also places emphasis on compatibility with the complementary BLE Android application that was developed for the custom device, but it does not cover the development of the application itself. The software is made from the ground up, because no suitable existing project was found that could be used as its basis. The result of the thesis is functional control software that can be used on the custom-made devices or as a basis for a similar project.

Versatile Hardware Framework for Elliptic Curve Cryptography

Author
Vít Mašek
Year
2022
Type
Bachelor thesis
Supervisor
Dr.-Ing. Martin Novotný
Reviewers
Ing. Vojtěch Miškovský, Ph.D.
Summary
This thesis proposes a versatile hardware framework for elliptic curve cryptography. The framework supports modular arithmetics with up to 256-bit general modulus and optimized arithmetic for P-256, Ed25519, and Curve25519 curves, enabling easy implementation of various elliptic curve cryptography algorithms. Full elliptic curve and Edwards curve digital signature algorithms can be performed using this framework as well as the X25519 algorithm for Diffie-Hellman key exchange. Such a framework finds its application area in nowadays rapidly expanding field of hardware wallets or IoT devices. As the design is intended to be implemented in ASIC, it is designed to be area efficient. Individual hardware units are reused for several different calculations. The framework allows to implement several side-channel attack countermeasures, mainly masking techniques, even after the framework is designed.

Testability and Physical Security: The Cell-Level Approach

Author
Ing. Jan Bělohoubek
Year
2022
Type
Dissertation thesis
Supervisor
doc. Ing. Petr Fišer, Ph.D.
Reviewers
Prof. Dr. Amir Moradi; Prof. Dr.-Ing. Miloš Krstić; prof. Michel Renovell, Ph.D

Smart monitoring system

Author
Michal Žůrek
Year
2021
Type
Bachelor thesis
Supervisor
Ing. Miroslav Skrbek, Ph.D.
Reviewers
Ing. Martin Daňhel, Ph.D.
Summary
The goal of this thesis is to develop monitoring system which monitor environment using camera and transfers data of picture to cloud for further processing. Thesis targets security aspects of solution. The thesis describes possible opportunities to develop monitoring system using different approaches and describes their properties that results from selection. Thesis describes development of IoT device based on Azure Sphere platform which is connected to Microsoft Azure cloud, cloud application based on Azure services developed according to concept PaaS and user application presenting outputs from monitoring system to user. The thesis also describes some issues associated with development on the Azure Sphere platform and their possible solutions.

Smart mirror prototype

Author
Jakub Zahradník
Year
2021
Type
Bachelor thesis
Supervisor
Ing. Martin Daňhel, Ph.D.
Reviewers
doc. Ing. Ivan Šimeček, Ph.D.
Summary
This bachelor thesis deals with the design and implementation of a functional prototype of a smart mirror. The analytical part of this work is devoted to a detailed analysis of already completed projects, whether by technology enthusiasts or products available on the market. The possible benefits or negatives of the investigated solutions are evaluated in this analytical part of work, either from the point of view of the materials used, technologies or the way of user control. In the next phase of the analytical part, possible SW platforms and HW products are considered, which could be used for the implementation of a smart mirror. Great attention is paid especially to the selection of suitable display components - various types of glasses and displays are discussed here. The practical part of this work deals with the creation of a functional prototype of a smart mirror. The construction of the mirror is unique, frameless and is designed to offer the user the largest possible display area for information and at the same time a modern design with voice control. The created prototype is based on the Raspberry Pi platform, and also are listed here expandable modules for light control. The steps for installing the individual SW platforms HomeAsistant, MagicMirror^2 and the voice assistant Kalliope are described. Part of the work is also a procedure how to configure individual platforms, solve possible problems and also it is indicated the way of possible expansion or use of the designed mirror in a smart home. Finally, the prototype is thoroughly tested to ensure the functional reliability of the entire system.

CPU simulation in SystemVerilog

Author
Vojtěch Jílek
Year
2022
Type
Master thesis
Supervisor
Ing. Martin Kohlík, Ph.D.
Reviewers
Ing. Jiří Kašpar
Summary
This thesis deals with design of simulation environments for processor simulation in the SystemVerilog language. The UVM library, its register model and the QuestaSim development environment are used to simulate processors. In this work, a simulation environment for two processors is designed - a singlecycle processor and a pipeline processor. Part of this thesis is a brief text with a description of several problems that a novice developer may encounter when using the registry model of the UVM library.

Adaptive mitigation of DDoS attacks based on online analysis

Author
Pavel Šiška
Year
2021
Type
Master thesis
Supervisor
doc. Ing. Tomáš Čejka, Ph.D.
Reviewers
Ing. Simona Fornůsek, Ph.D.
Summary
This thesis deals with design and implementation of the tool for online packet analysis of network traffic. Main goal is to provide necessarily informations for administrator to ensure, that he can set defence mechanisms for mitigation of DDoS attacks. Tool provides overview of actual structure of the network traffic. It can also identify and recommend mitigation rules to suppress DDoS attack, based on characteristics of volumetric DDoS attacks. Tool for saving data for analysis is using special probability data structures, called sketch, which can effectively store great amount of data with low memory requirements. Performance and functionality of the tool was tested in lab over test data with speed reaching up to 100 Gb/s.

Side-channel analysis of Rainbow post-quantum signature

Author
David Pokorný
Year
2021
Type
Master thesis
Supervisor
Ing. Petr Socha
Reviewers
Dr.-Ing. Martin Novotný
Summary
Rainbow, a layered multivariate quadratic digital signature, is a candidate for~standardization by National institute of standards and technology (NIST). In~this paper, we present a CPA side-channel attack on the submitted 32-bit reference implementation. We evaluate the attack on an STM32F3 ARM microcontroller. After a successful attack, we propose countermeasures against side-channel attacks. Countermeasures are implemented and evaluated using leakage assessment.

Datalogger for ionizing radiation spectrum measuring equipment

Author
Libor Kuchař
Year
2021
Type
Master thesis
Supervisor
Ing. Filip Štěpánek
Reviewers
Ing. Martin Kohlík, Ph.D.
Summary
Datalogger is a device that records data over time. The content of this thesis discusses how to appropriately design and implement a homemade datalogger suitable for measuring the spectrum of ionizing radiation. Within the assignment, the requirements for functionality and technical equipment / design of the product are discussed. The realisation consists of designing of a printed circuit board, embedded firmware for the STM32 microcontroller and the Wi-Fi module ESP-01. It also includes implementation of the service PC application for Windows 10. Physical background of the measurement of the ionizing radiation spectrum as well as details regarding the design, realization, and testing of the final product are described in the text.

Detection of IoT Malware in Computer Networks

Author
Daniel Uhříček
Year
2021
Type
Master thesis
Supervisor
Ing. Karel Hynek, Ph.D.
Reviewers
Ing. Jiří Dostál, Ph.D.
Summary
This master thesis deals with the problematics of IoT malware and the possibilities of its detection in computer networks using flow-based monitoring concepts. We exhibit solutions for each of the identified critical aspects of IoT malware network behavior separately. Furthermore, we propose a novel method to discover infected devices using a combination of network indicators. The proposed detection method was implemented in the form of a software prototype capable of processing real network traffic as part of the NEMEA system. The final solution was evaluated both on anonymized captures and up-to-date malware samples.

FPGA Acceleration of the Baby Variant of the WTFHE Scheme

Author
Pavel Chytrý
Year
2021
Type
Master thesis
Supervisor
Dr.-Ing. Martin Novotný
Reviewers
Ing. Jakub Klemsa
Summary
With the rise of cloud compute services, the privacy of user's data is often put into question, as the service provider has full access to it. This is further exacerbated by facilities that hold private data, but lack the computational power to run their own research - namely hospitals. A Fully Homomorphic Encryption (FHE) could be a solution to this problem as it can evaluate arbitrary functions over encrypted data without the need for decryption on the Cloud service provider's side. Since the breakthrough by Gentry et al. in 2009, this field is very active with Chilloti et al. recently introducing the scheme called TFHE. TFHE scheme has been shown to be suitable for securing Machine Learning as a Service (MLaaS). TFHE in its original form only works with one-bit plaintext space, however, several improvements allow the usage of multivalue plaintext space. This improved version was codenamed netWork-ready TFHE (WTHE). In general, (W)TFHE Schemes implemented in software are several orders of magnitude slower than the commonly used encryption schemes. This thesis serves as a case study to determine the feasibility of accelerating the WTFHE Scheme with an FPGA. Our contributions consist of designing an FPGA accelerator capable of simple Neural Network evaluation, measuring its performance compared to the software setup, discovering resource requirements, and the potential of scalability.

Hardware tool for precise targeting of the camera view in the room

Author
Zuzana Jiránková
Year
2021
Type
Master thesis
Supervisor
Ing. Jakub Novák
Reviewers
Dr.-Ing. Martin Novotný
Summary
The aim of the work is to create a hardware system to focus the view of industrial camera in the sense of getting higher resolution in area of interest. A solution to use two cameras was chosen. The first one is an overview camera and the second one is a detail camera, which gaze is aimed by a mirror tilted in two axis. The created solution enables to aim to a wanted object from an overview camera and retrieve its detail in higher resolution by the detail camera. The main result of the work is the created hardware system and its firmware to control tilting of the mirror.

Advanced error control codes using Wolfram Mathematica

Author
Stanislav Koleník
Year
2021
Type
Master thesis
Supervisor
Ing. Pavel Kubalík, Ph.D.
Reviewers
Ing. Jiří Buček, Ph.D.
Summary
Error-control codes are used in digital communication systems to protect data against noise during transmission. There are many methods to achieve this kind of protection, all are mathematical in nature. A set of teaching materials in the Wolfram Mathematica computing system has been developed in the past to demonstrate some of these methods. The aim of this work is to extend the set by adding some more advanced codes.

Robust flash memory bootloader for a microcontroller over near field communication

Author
Jitka Seménková
Year
2021
Type
Master thesis
Supervisor
Ing. Jiří Hušák
Reviewers
Ing. Robert Hülle, Ph.D.
Summary
This thesis includes the design and implementation of a flash memory bootloader for a RISC-V microcontroller. Communication is done over the NFC board NTAG5 link. Design and implementation of the communication are also present in this thesis. The created bootloader is robust, and its memory footprint is small. As a part of this thesis, an Android application was created to test the bootloader.

Autonomous Car Model Control

Author
Petr Kolář
Year
2021
Type
Master thesis
Supervisor
Ing. Miroslav Skrbek, Ph.D.
Reviewers
doc. Ing. Ivan Šimeček, Ph.D.
Summary
This thesis deals with controlling the autonomous vehicle, based on microcomputer Raspberry Pi. This vehicle model was improved with sensors for measuring distance and with incremental encoders for measuring travelled distance, speed and direction. Additionally, the vehicle was improved with more parts for improved driving properties and simplifying the use of the model. For sensor connections printed circuit boards were created. The car's control software was also modified. A~complex autonomous driving system was created for the model, which included a track with road signs, ultrasound car localisation and an application for track recognition. Recognition is performed both in a traditional way (openCV) and with the use of neural networks. The driving system and the modified model were tested on different model tracks.

Low-Latency Optimizations and Architectures for Compression Algorithms implemented in (Programmable) Hardware

Author
Ing. Matěj Bartík
Year
2021
Type
Dissertation thesis
Supervisor
Dr. Ing. Sven Ubik
Reviewers
doc. Ing. Jan Kořenek, Ph.D.; doc. Ing. Jaroslav Zdrálek, Ph.D; Dr. Dirk Koch